Memory Summary For ANDREW-PC
Number of Memory Devices: 4 Total Physical Memory: 8191 MB (8192 MB)
Total Available Physical Memory: 6241 MB
Memory Load: 23%
| Item | Module #1 | Module #2 | Module #3 | Module #4 |
|---|
| Ram Type |
DDR2 |
DDR2 |
DDR2 |
DDR2 |
| Standard Name |
DDR2-800 |
DDR2-800 |
DDR2-800 |
DDR2-800 |
| Module Name |
PC2-6400 |
PC2-6400 |
PC2-6400 |
PC2-6400 |
| Memory Capacity (MB) |
2048 |
2048 |
2048 |
2048 |
| Bus Clockspeed (Mhz) |
400.00 |
400.00 |
400.00 |
400.00 |
| Jedec Manufacture Name |
Qimonda |
A-DATA Technology |
Samsung |
A-DATA Technology |
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| SPD Revision |
1.2 |
1.2 |
1.2 |
1.2 |
| Registered |
No |
No |
No |
No |
| ECC |
No |
No |
No |
No |
| DIMM Slot # |
1 |
2 |
3 |
4 |
| Manufactured |
Year 0 |
Year 0 |
Year 0 |
Year 0 |
| Module Part # |
64T256020EU2.5C2 |
DQVE1B16 |
M3 78T5663RZ3-CF7 |
|
| Module Revision |
0x112A |
0x0 |
0x3352 |
0x0 |
| Module Serial # |
0x301F51E |
0x0 |
0x64874F47 |
0x0 |
| Module Manufacturing Location |
68 |
0 |
2 |
1 |
| # of Row Addressing Bits |
14 |
14 |
14 |
14 |
| # of Column Addressing Bits |
10 |
10 |
10 |
10 |
| # of Banks |
8 |
8 |
8 |
8 |
| # of Ranks |
2 |
2 |
2 |
2 |
| Device Width in Bits |
8 |
8 |
8 |
8 |
| Bus Width in Bits |
64 |
64 |
64 |
64 |
| Module Voltage |
SSTL 1.8V |
SSTL 1.8V |
SSTL 1.8V |
SSTL 1.8V |
| CAS Latencies Supported |
4 5 6 |
3 4 5 |
4 5 6 |
4 5 6 |
| Timings @ Max Frequency |
6-6-6-18 |
5-5-5-18 |
6-6-6-18 |
6-6-6-18 |
| Minimum Clock Cycle Time, tCK (ns) |
2.500 |
2.500 |
2.500 |
2.500 |
| Minimum CAS Latency Time, tAA (ns) |
15.000 |
12.500 |
15.000 |
15.000 |
| Minimum RAS to CAS Delay, tRCD (ns) |
15.000 |
12.500 |
15.000 |
15.000 |
| Minimum Row Precharge Time, tRP (ns) |
15.000 |
12.500 |
15.000 |
15.000 |
| Minimum Active to Precharge Time, tRAS (ns) |
45.000 |
45.000 |
45.000 |
45.000 |
| Minimum Row Active to Row Active Delay, tRRD (ns) |
7.500 |
7.500 |
7.500 |
7.500 |
| Minimum Auto-Refresh to Active/Auto-Refresh Time, tRC (ns) |
60.000 |
57.500 |
60.000 |
60.000 |
| Minimum Auto-Refresh to Active/Auto-Refresh Command Period, tRFC (ns) |
127.500 |
127.500 |
127.500 |
127.500 |
| |
|
|
|
|
| DDR2 Specific SPD Attributes |
|
|
|
|
| Data Access Time from Clock, tAC (ns) |
0.400 |
0.400 |
0.400 |
0.400 |
| Clock Cycle Time at Medium CAS Latency (ns) |
3.000 |
3.750 |
3.000 |
3.000 |
| Data Access Time at Medium CAS Latency (ns) |
0.450 |
0.500 |
0.450 |
0.450 |
| Clock Cycle Time at Short CAS Latency (ns) |
3.750 |
5.000 |
3.750 |
3.750 |
| Data Access Time at Short CAS Latency (ns) |
0.500 |
0.600 |
0.500 |
0.500 |
| Maximum Clock Cycle Time (ns) |
8.000 |
8.000 |
8.000 |
8.000 |
| Write Recover Time, tWR (ns) |
15.000 |
15.000 |
15.000 |
15.000 |
| Internal Write to Read Command Delay, tWTR (ns) |
7.500 |
7.500 |
7.500 |
7.500 |
| Internal Read to Precharge Command Delay, tRTP (ns) |
7.500 |
7.500 |
7.500 |
7.500 |
| Address/Command Setup Time Before Clock, tIS (ns) |
0.170 |
0.180 |
0.170 |
0.180 |
| Address/Command Hold Time After Clock, tIH (ns) |
0.250 |
0.250 |
0.250 |
0.250 |
| Data Input Setup Time Before Strobe, tDS (ns) |
0.050 |
0.050 |
0.050 |
0.050 |
| Data Input Hold Time After Strobe, tDH (ns) |
0.120 |
0.130 |
0.120 |
0.130 |
| Maximum Skew Between DQS and DQ Signals (ns) |
0.200 |
0.200 |
0.200 |
0.200 |
| Maximum Read Data hold Skew Factor (ns) |
0.240 |
0.240 |
0.240 |
0.240 |
| PLL Relock Time (ns) |
0.000 |
0.000 |
0.000 |
0.000 |
| DRAM Package Type |
Planar |
Planar |
Planar |
Planar |
| Burst Lengths Supported |
4 8 |
4 8 |
4 8 |
4 8 |
| Refresh Rate |
Reduced (7.8us) |
Reduced (7.8us) |
Reduced (7.8us) |
Reduced (7.8us) |
| # of PLLS on DIMM |
0 |
0 |
0 |
0 |
| FET Switch External Enable |
No |
No |
No |
No |
| Analysis Probe Installed |
No |
No |
No |
No |
| Weak Driver Supported |
Yes |
Yes |
Yes |
Yes |
| 50 Ohm ODT Supported |
Yes |
Yes |
Yes |
Yes |
| Partial Array Self Refresh Supported |
Yes |
No |
Yes |
No |
| Module Type |
UDIMM |
UDIMM |
UDIMM |
UDIMM |
| Module Height (mm) |
30.0 |
30.0 |
30.0 |
30.0 |