RAMMon v1.0 Build: 1002 built with SysInfo v1.0 Build: 1019
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Memory Summary For JEFFERSON-PC
Number of Memory Devices: 2	Total Physical Memory: 3006 MB (4096 MB)
				Total Available Physical Memory: 1118 MB
				Memory Load: 62%	

ItemSlot #1Slot #2
Ram Type DDR2 DDR2
Standard Name DDR-667 DDR-667
Module Name PC-5300 PC-5300
Memory Capacity (MB) 2048 2048
Bus Clockspeed (Mhz) 333.33 333.33
Jedec Manufacture Name Kingston Kingston
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SPD Revision 1.2 1.2
Registered No No
ECC No No
DIMM Slot # 1 2
Manufactured Year 0 Year 0
Module Part # 2G-UDIMM 2G-UDIMM
Module Revision 0x0 0x0
Module Serial # 0x83149751 0x47CCE562
Module Manufacturing Location 3 5
# of Row Addressing Bits 14 14
# of Column Addressing Bits 10 10
# of Banks 8 8
# of Ranks 2 2
Device Width in Bits 8 8
Bus Width in Bits 64 64
Module Voltage SSTL 1.8V SSTL 1.8V
CAS Latencies Supported 3 4 5 3 4 5
Timings @ Max Frequency 5-5-5-15 5-5-5-15
Minimum Clock Cycle Time, tCK (ns) 3.000 3.000
Minimum CAS Latency Time, tAA (ns) 15.000 15.000
Minimum RAS to CAS Delay, tRCD (ns) 15.000 15.000
Minimum Row Precharge Time, tRP (ns) 15.000 15.000
Minimum Active to Precharge Time, tRAS (ns) 45.000 45.000
Minimum Row Active to Row Active Delay, tRRD (ns) 7.500 7.500
Minimum Auto-Refresh to Active/Auto-Refresh Time, tRC (ns) 60.000 60.000
Minimum Auto-Refresh to Active/Auto-Refresh Command Period, tRFC (ns) 127.500 127.500
DDR2 Specific SPD Attributes
Data Access Time from Clock, tAC (ns) 0.450 0.450
Clock Cycle Time at Medium CAS Latency (ns) 3.750 3.750
Data Access Time at Medium CAS Latency (ns) 0.500 0.500
Clock Cycle Time at Short CAS Latency (ns) 5.000 5.000
Data Access Time at Short CAS Latency (ns) 0.600 0.600
Maximum Clock Cycle Time (ns) 8.000 8.000
Write Recover Time, tWR (ns) 15.000 15.000
Internal Write to Read Command Delay, tWTR (ns) 7.500 7.500
Internal Read to Precharge Command Delay, tRTP (ns) 7.500 7.500
Address/Command Setup Time Before Clock, tIS (ns) 0.200 0.200
Address/Command Hold Time After Clock, tIH (ns) 0.270 0.270
Data Input Setup Time Before Strobe, tDS (ns) 0.100 0.100
Data Input Hold Time After Strobe, tDH (ns) 0.170 0.170
Maximum Skew Between DQS and DQ Signals (ns) 0.240 0.240
Maximum Read Data hold Skew Factor (ns) 0.220 0.220
PLL Relock Time (ns) 0.000 0.000
DRAM Package Type Planar Planar
Burst Lengths Supported 4 8 4 8
Refresh Rate Reduced (7.8us) Reduced (7.8us)
# of PLLS on DIMM 0 0
FET Switch External Enable No No
Analysis Probe Installed No No
Weak Driver Supported Yes Yes
50 Ohm ODT Supported Yes Yes
Partial Array Self Refresh Supported No No
Module Type UDIMM UDIMM
Module Height (mm) 30.0 30.0