Memory Summary For SOUNDWAVE
Number of Memory Devices: 2 Total Physical Memory: 2046 MB (0 MB)
Total Available Physical Memory: 1378 MB
Memory Load: 32%
| Item | Slot #1 | Slot #2 | Slot #3 | Slot #4 |
|---|
| Ram Type |
DDR2 |
Not Populated |
DDR2 |
Not Populated |
| Maximum Clock Speed (MHz) |
266.67 (JEDEC) |
|
266.67 (JEDEC) |
|
| Maximum Transfer Speed (MHz) |
DDR2-533 |
|
DDR2-533 |
|
| Maximum Bandwidth (MB/s) |
PC2-4200 |
|
PC2-4200 |
|
| Memory Capacity (MB) |
1024 |
|
1024 |
|
| Jedec Manufacture Name |
Hynix Semiconductor (Hyundai Electronics) |
|
Hynix Semiconductor (Hyundai Electronics) |
|
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|
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|
| SPD Revision |
1.2 |
|
1.2 |
|
| Registered |
No |
|
No |
|
| ECC |
No |
|
No |
|
| DIMM Slot # |
1 |
|
3 |
|
| Manufactured |
Year 0 |
|
Year 0 |
|
| Module Part # |
HYMP512U64BP8-C4 |
|
HYMP512U64BP8-C4 |
|
| Module Revision |
0x4141 |
|
0x4141 |
|
| Module Serial # |
0x6135 |
|
0x2135 |
|
| Module Manufacturing Location |
1 |
|
1 |
|
| # of Row Addressing Bits |
14 |
|
14 |
|
| # of Column Addressing Bits |
10 |
|
10 |
|
| # of Banks |
4 |
|
4 |
|
| # of Ranks |
2 |
|
2 |
|
| Device Width in Bits |
8 |
|
8 |
|
| Bus Width in Bits |
64 |
|
64 |
|
| Module Voltage |
SSTL 1.8V |
|
SSTL 1.8V |
|
| CAS Latencies Supported |
3 4 5 |
|
3 4 5 |
|
| Timings @ Max Frequency (JEDEC) |
5-4-4-12 |
|
5-4-4-12 |
|
| Maximum frequency (MHz) |
266.67 |
|
266.67 |
|
| Maximum Transfer Speed (MHz) |
DDR2-533 |
|
DDR2-533 |
|
| Maximum Bandwidth (MB/s) |
PC2-4200 |
|
PC2-4200 |
|
| Minimum Clock Cycle Time, tCK (ns) |
3.750 |
|
3.750 |
|
| Minimum CAS Latency Time, tAA (ns) |
18.750 |
|
18.750 |
|
| Minimum RAS to CAS Delay, tRCD (ns) |
15.000 |
|
15.000 |
|
| Minimum Row Precharge Time, tRP (ns) |
15.000 |
|
15.000 |
|
| Minimum Active to Precharge Time, tRAS (ns) |
45.000 |
|
45.000 |
|
| Minimum Row Active to Row Active Delay, tRRD (ns) |
7.500 |
|
7.500 |
|
| Minimum Auto-Refresh to Active/Auto-Refresh Time, tRC (ns) |
60.000 |
|
60.000 |
|
| Minimum Auto-Refresh to Active/Auto-Refresh Command Period, tRFC (ns) |
105.000 |
|
105.000 |
|
| |
|
|
|
|
| DDR2 Specific SPD Attributes |
|
|
|
|
| Data Access Time from Clock, tAC (ns) |
0.500 |
|
0.500 |
|
| Clock Cycle Time at Medium CAS Latency (ns) |
3.750 |
|
3.750 |
|
| Data Access Time at Medium CAS Latency (ns) |
0.500 |
|
0.500 |
|
| Clock Cycle Time at Short CAS Latency (ns) |
5.000 |
|
5.000 |
|
| Data Access Time at Short CAS Latency (ns) |
0.600 |
|
0.600 |
|
| Maximum Clock Cycle Time (ns) |
8.000 |
|
8.000 |
|
| Write Recover Time, tWR (ns) |
15.000 |
|
15.000 |
|
| Internal Write to Read Command Delay, tWTR (ns) |
7.500 |
|
7.500 |
|
| Internal Read to Precharge Command Delay, tRTP (ns) |
7.500 |
|
7.500 |
|
| Address/Command Setup Time Before Clock, tIS (ns) |
0.250 |
|
0.250 |
|
| Address/Command Hold Time After Clock, tIH (ns) |
0.370 |
|
0.370 |
|
| Data Input Setup Time Before Strobe, tDS (ns) |
0.100 |
|
0.100 |
|
| Data Input Hold Time After Strobe, tDH (ns) |
0.220 |
|
0.220 |
|
| Maximum Skew Between DQS and DQ Signals (ns) |
0.300 |
|
0.300 |
|
| Maximum Read Data hold Skew Factor (ns) |
0.280 |
|
0.280 |
|
| PLL Relock Time (ns) |
0.000 |
|
0.000 |
|
| DRAM Package Type |
Planar |
|
Planar |
|
| Burst Lengths Supported |
4 8 |
|
4 8 |
|
| Refresh Rate |
Reduced (7.8us) |
|
Reduced (7.8us) |
|
| # of PLLS on DIMM |
0 |
|
0 |
|
| FET Switch External Enable |
No |
|
No |
|
| Analysis Probe Installed |
No |
|
No |
|
| Weak Driver Supported |
Yes |
|
Yes |
|
| 50 Ohm ODT Supported |
Yes |
|
Yes |
|
| Partial Array Self Refresh Supported |
Yes |
|
Yes |
|
| Module Type |
UDIMM |
|
UDIMM |
|
| Module Height (mm) |
30.0 |
|
30.0 |
|