Where Venice stands in the calendar
AMD announced the 6th Gen EPYC "Venice" processors in July 2026. It said they were in production, with the SP7 9006 series shipping in Q4 2026, SP8 parts in the first half of 2027, and the 9006X HPC parts in the second half of 2027. In May, AMD announced that Venice production was ramping on TSMC's 2nm process in Taiwan, with Arizona capacity planned later. Tom's Hardware's review, published on November 10, covers the first SP7 chips. Consumer "Olympic Ridge" parts are expected next year.
What changed in Zen 6
Tom's Hardware describes Zen 6 as an expansion of Zen 5, not a clean-sheet redesign. AMD says the architecture is built on TSMC's N2P node. Details reported in the review:
- IPC: AMD claims a 27% average uplift over Zen 5 in enterprise, cloud and AI workloads. The reviewer warns against applying that figure to every workload. AMD's baseline was fixed-frequency Zen 5 against a 16-core Zen 6c configuration.
- Core internals: The op cache grows to 6.75K entries and the return address stack to 64 entries. Integer schedulers are split, and the physical register file grows to 352 entries. The vector engine adds native AVX-512 FP16 and can do two 512-bit or four 256-bit loads.
- Cache: The 48 KB L1 data cache and 1 MB private L2 carry over from Zen 5.
- Chiplets: A standard CCD scales to 12 cores, up from 8. A Zen 6c CCD scales to 32, up from 16. Zen 6c doubles L3 per core to 4 MB, so a Zen 6c CCD carries 128 MB of L3.
- Clocks: The top CCD frequency moves from 5.0 to 5.3 GHz on Zen 6 and from 3.7 to 4.1 GHz on Zen 6c.
Platform: SP7, SP8, memory and I/O
SP7 is a larger socket than SP5. It uses two I/O dies to provide 16 DDR5 channels, up to 12,800 MT/s with MRDIMMs or 8,000 MT/s with RDIMMs. AMD claims up to 1.6 TB/s per socket with MRDIMMs. The review says SP7 gives up PCIe 6.0 lanes compared with SP8: 96 lanes in 1P and up to 128 in 2P. SP8 is a smaller socket with eight memory channels and more PCIe 6.0 lanes. Both platforms support CXL 3.1.
AMD also added three management features, which the review attributes to AMD and did not test:
- UPP (Unified Power Provisioning) allocates power across the whole platform. AMD's example is fitting 18 servers into a rack where 16 fit before.
- UBPS (Utilization Based Power Scaling) scales platform power to match the workload.
- FAST (Frequency Adaptive Spectrum Technology) uses firmware policy and telemetry to set different frequency tiers within one socket. AMD's example splits a 96-core part into a 32-core premium group and a 64-core batch group.
The review also covers MEXT, AMD's flash-as-DRAM technology delivered as a Linux kernel module. AMD claims it holds 95% of an EDA application's performance with half the DRAM. Those are AMD's internal numbers, and the review says it only suits certain workloads.
The two chips tested
| Chip | Cores / threads (per socket) | Base / boost | L3 | Rated power |
|---|---|---|---|---|
| EPYC 9996 | 256 / 512 | 2.55 / 4.1 GHz | 1,024 MB | 600 W |
| EPYC 9686F | 96 / 192 | 3.4 / 5.0 GHz | 384 MB | 500 W |
Both can be configured between 400 W and 600 W. The 9996 is the throughput part. The 9686F is the frequency-optimized part and the closest rival to Vera.
The test platforms were not identical, so these are whole-system comparisons. The Venice systems used 2 TB of DDR5-12800 MRDIMMs. The Zen 5 comparison systems used 1.5 TB of DDR5-6000 RDIMMs. The Xeon 6980P used DDR5-8800 MRDIMMs. Vera used 1.5 TB of LPDDR5 SOCAMM2. Tests ran on Ubuntu Server 26.04 with Linux 7.0. The Venice chips used GCC 16 and the rest used GCC 15.2. The reviewer says regression testing found only minor differences.
What the benchmarks showed
The SPEC CPU 2026 figures are labeled estimates. They come from real runs that were not submitted to SPEC.
- Integer throughput: The 2P EPYC 9996 beat the 2P EPYC 9965 by 93%. Much of that comes from 1,024 threads against 768. The 2P 9686F was 19% ahead of a 2P EPYC 9755 and 17% ahead of Vera.
- Floating point: The Venice systems more than doubled the Zen 5 scores. The 9686F led Vera by 40%.
- Python: In PyBench the 9686F was 32% faster than Vera. The 9996 was 14% ahead. The review notes that about 900 MHz of the 9686F's 35% lead over the 9755 comes from its higher boost clock.
- Rendering and compression: The 9996 finished the Blender Barbershop scene 35% faster than the 9965. Vera is absent from the Blender results because there is no native Arm build. AMD led in 7-Zip and for most of the zstd results.
- Java and HPC: The 9686F led Vera by 92% in Java SciMark. In CloverLeaf it was more than twice as fast as Vera.
Where Venice did not win
- Memory bandwidth: In STREAM, AMD led Vera by 11% to 19% under one process-binding policy. With the "spread" policy, Vera came out on top. Vera also led the MBW test at larger array sizes.
- Cold-cache databases: In ClickHouse, Vera reached peak performance from a cold cache while the x86 chips needed warm caches. The 9996 also regressed against the 9965, which the review blames on cache coherency at high core counts.
- Other tests: Vera kept the top spot in C-Ray and Octave, and the networkx result was a tie.
- Intel: The review says Diamond Rapids is due next year and could change the picture.
AMD's own numbers
AMD publishes its own comparisons, and they should be read separately from the review. In its newsroom material, AMD reports an estimated SPECrate 2026 integer score of 2,070 for a 2P EPYC 9996 against 925 for a 2P Nvidia Vera, about 2.2 times. AMD describes those as preliminary estimates dated July 22, 2026, and says results may vary. Against the Xeon 6980P, AMD's footnotes report gains of up to 3.7 times in NGINX and 2.9 times in Redis. AMD ran those tests itself, on single-socket systems.
Practical takeaways
- Match the SKU to the workload. The 9996 suits many concurrent jobs, such as dense virtualization and batch work. The 9686F suits single-thread-sensitive and HPC work.
- Treat the 93% figure as a throughput result, not an IPC result.
- Budget for MRDIMMs. Many of the review's headline results used 12,800 MT/s memory on all 16 channels. RDIMM-based systems top out at 8,000 MT/s.
- Check the OS. The review ran Ubuntu Server 26.04 on Linux 7.0 with GCC 16. These are Linux results, with no Windows Server benchmarks in the review.
- Wait on SP8 and Verano if you need lower-core enterprise parts or LPDDR memory.
Tom's Hardware's results are from AMD-supplied reference platforms, and AMD gave the reviewer early access. That is standard practice, but it is worth remembering, along with the mismatched memory configurations across systems. The review is not proof that Venice wins everywhere. It does show that Venice is a step up from Turin and a serious rival to Vera, and that Vera still wins some memory-bound and cold-cache workloads.