That is the important distinction behind the announcements first reported by The Register from this week’s AI Infra Summit in Santa Clara. The companies are attacking a real bottleneck—accelerators waiting on data, synchronization, and collective operations—but their announcements represent architecture, validation hardware, and funding more than an immediate procurement alternative to Nvidia’s mature NVLink Switch systems.
For enterprise AI teams, cloud operators, and systems administrators, this is still meaningful news. The networking layer is becoming a design constraint for large training clusters and distributed inference, particularly mixture-of-experts workloads that generate heavy all-to-all traffic. The practical takeaway is more modest than the launch rhetoric: alternatives are beginning to define the interfaces and management model customers will need, but buyers should treat them as roadmap evaluation candidates rather than replacements for an NVLink-based deployment planned this year.
Cornelis moves scale-up support onto its future roadmap
Cornelis announced Active Compute Fabric, or ACF, on September 14 alongside approximately $205 million in funding and a collaboration with Qualcomm. Cornelis says the architecture will combine lossless transport, collective-operation acceleration, and programmable processing inside the network fabric, rather than leaving every communication task to GPUs, CPUs, and host software.
The premise is credible. Large AI jobs spend meaningful time on communication: AllReduce and related collectives synchronize model parameters during training, while inference systems increasingly shuttle key-value cache data and route tokens among specialist models. Nvidia’s own NVLink Switch includes SHARP engines for in-network reductions and multicast acceleration, so offloading parts of the collective workload to switches is an established capability, not a new category invented by Cornelis.
Cornelis’ public material also contains the first material limitation that buyers need to understand. Its shipping CN5000 product is a scale-out technology based on Omni-Path. The announced CN6000 is sampling with customers and is expected to become more widely available in the fourth quarter of 2026; it adds RoCEv2 and Ultra Ethernet compatibility through a multi-protocol SuperNIC, but Cornelis says the end-to-end fabric remains Omni-Path.
Native UALink and Ethernet for Scale-Up Networking, or ESUN, support is instead assigned to the future CN7000. Cornelis describes the collective-acceleration and programmable-compute portions of ACF as “coming soon,” and explicitly characterizes CN7000 specifications as design targets subject to change. In other words, the company has announced its scale-up direction and the functions it wants the fabric to execute, but has not announced a generally available UALink switch that an administrator can order, integrate, and operate today.
That is not a trivial caveat. An Ethernet-compatible network interface at the server edge is useful for migration and interoperability, but it does not make an Omni-Path fabric an open Ethernet or UALink deployment. Cornelis’ contention that the architecture is open refers to the standards it intends to support and the range of accelerators it wants to serve; it should not be read as a claim that customers can substitute any standards-compliant switch into the middle of a Cornelis fabric.
The utilization math is a model, not a benchmark
Cornelis says its modeling of a 100,000-GPU system finds that roughly half of GPU time is spent waiting for data, representing $1.68 billion in annual unused capacity and 500 GWh of electricity. The company’s own disclosure says this figure assumes $4 per GPU-hour, 8,400 operating hours annually, and 50 percent unproductive GPU time.
The arithmetic makes the claim more understandable, but it also shows why it cannot be used as a universal savings forecast. A training cluster with frequent all-reduce synchronization, oversubscribed links, poor job placement, and immature communication libraries may leave significant capacity stranded. A system with a different model architecture, a well-tuned topology, or lower accelerator utilization will produce a very different result.
Network World and TechCrunch separately reported that Cornelis is focusing its pitch on programmable in-network work and reducing accelerator idle time. Neither report establishes independent performance results for ACF’s future scale-up implementation. Cornelis’ own product pages cite internal benchmarks for several performance comparisons and label the newer programmable functions as forthcoming.
The better reading is that Cornelis is trying to make the network a programmable execution layer at a moment when AI clusters are treating communication as a first-class resource. It has not yet demonstrated that its announced hardware will deliver its modeled savings across customer workloads. Organizations considering the platform should require workload-specific proof using their model parallelism, batch sizes, collective library, failure behavior, and actual rack topology.
Delos is selling an integration blueprint before it sells a fabric
Delos Data made its own entrance at the summit on September 15, announcing more than $100 million in funding and its Nonstop AI reference architecture. Unlike Cornelis, Delos is not primarily presenting a switch-fabric architecture. It is proposing a stack spanning software, servers, NICs, near-packaged optics, and accelerator-adjacent I/O interfaces.
Its most ambitious element is an I/O die intended to provide more than 30 Tbps of aggregate bandwidth. Delos told The Register that the component is protocol-agnostic, with the goal of allowing accelerator designers to use UALink, ESUN, or another protocol rather than inheriting one vendor’s locked interface. That design position could appeal to hyperscalers and custom-silicon programs that want an external specialist to solve high-speed I/O while they concentrate engineering budgets on compute and memory.
However, a die that sits in an accelerator package is not an aftermarket upgrade. It requires a chip designer to license, integrate, validate, package, and manufacture it alongside a new accelerator. The headline bandwidth therefore describes a potential future design point, not a card that can be inserted into an existing Nvidia, AMD, or custom AI server.
HPCwire reports that Delos has a PCIe development and test card called Morpheus available now, intended to let customers validate its IP across network topologies. It also reports that Delos’ Asterion server is expected to sample to customers at the end of 2026. Delos’ public announcement, meanwhile, describes the newly announced Data Interface as part of a reference architecture and says its funding will accelerate product development and sales. It does not provide public availability dates for the high-bandwidth I/O die, near-packaged optics module, or proposed 400-plus-Gbps NIC.
That leaves Delos at an earlier commercial stage than the fundraising total might suggest. Morpheus may give prospective partners a way to test the company’s direction, but the core proposition depends on design wins that will take product cycles to appear in production accelerators and systems.
Open specifications now have real management requirements
The industry’s standards work is more concrete than the new hardware announcements. The UALink Consortium has published its 200G 1.0 specification for scale-up connections among accelerators and switches, stating that it supports up to 1,024 accelerators in an AI pod. It has also published a Common 2.0 specification that introduces in-network compute, plus chiplet and manageability specifications.
The manageability piece deserves more attention than the raw bandwidth claims. UALink’s published management specification calls for centralized control and management planes using technologies including gNMI, YANG, SAI, and Redfish. For operators, that is the basis for inventory, configuration consistency, telemetry, fault isolation, and automation—the work that determines whether an “open” AI fabric can be run safely at scale.
It also means a standards-compliant physical link alone will not create a multi-vendor AI pod. Customers will still need compatible accelerator firmware, NIC drivers, switch software, collective communication libraries, failure-recovery behavior, and validated topology guidance. Cornelis and Delos both make resilience part of their pitch, including dynamic rerouting and recovery after link failures. Neither announcement supplies the public interoperability matrix or operational runbook that would let a buyer compare those claims with Nvidia’s integrated system behavior.
Nvidia is not standing still while those pieces come together. Its sixth-generation NVLink is specified at 3 TB/s per GPU on Vera Rubin, with NVLink Switch connecting 72 GPUs in a non-blocking rack fabric. Nvidia has also expanded NVLink Fusion, which brings semi-custom CPUs and ASICs into its rack-scale architecture. The proprietary boundary has become less absolute, but Nvidia still supplies the integrated networking, switching, software, and validated system design around the interconnect.
What AI infrastructure teams should do now
The announcements make the market more competitive, but they do not change the immediate buying decision for a cluster arriving in 2026. Existing designs should be evaluated on delivered systems, supported accelerator combinations, and proven operational tooling—not on future port speeds or projected GPU-hour savings.
Teams evaluating Cornelis should ask exactly which workload functions run on shipping CN5000 and CN6000 hardware, which functions require CN7000, and whether their deployment would operate as Omni-Path end to end. They should also ask for test results from their preferred collective stack rather than assuming UALink or Ultra Ethernet compatibility translates directly into application performance.
Teams engaging Delos should separate the available Morpheus validation card from the components that require accelerator-package integration. The questions are whether a specific accelerator partner has committed to the I/O die, when silicon will sample, which optical modules and protocols will be supported, and how the company will expose telemetry and failure recovery to existing data-center automation.
Cornelis and Delos have made the same strategic bet: as AI systems move beyond a single eight-GPU server, interconnect design becomes too valuable to leave as a passive plumbing decision. Their announcements show that standards, programmable fabric functions, and accelerator-neutral I/O are moving from consortium documents into product plans. The actual replacement for NVLink will arrive only when those plans turn into interoperable systems that customers can deploy, monitor, repair, and expand without rebuilding the rack around one vendor.