Cleanroom technicians process silicon wafers while chip dies and packaging are showcased in a semiconductor fab.
CXMT has announced mass production of its fifth-generation DRAM manufacturing platform, claiming at least 50% more gross dies per wafer than its previous platform on a standardized capacity comparison. Unveiled on September 20 at the World Manufacturing Convention in Hefei, China, the G5 platform also underpins two new LPDDR5X products for smartphones and portable consumer electronics. It is a concrete memory-manufacturing development, but the announcement does not establish availability in Windows PCs or an immediate reduction in memory prices.

Reuters also reported CXMT’s mass-production announcement, describing it as a claimed breakthrough that could strengthen China’s position against Samsung Electronics, SK Hynix and Micron. The detailed manufacturing figures come from CXMT itself; they should be understood as the company’s claims rather than independently validated competitive benchmarks.

What the density improvement actually means​

Two important figures need separating: how many chips fit on a wafer, and how much memory each chip holds.

CXMT says G5 delivers at least 50% more gross dies per wafer, measured against its fourth-generation platform and normalized to an 8Gb capacity baseline. Separately, the company says its new LPDDR5X products provide 24Gb per die, a 50% capacity increase over equivalent previous-generation products. These are different comparisons, and they cannot be combined into a single claim that production has doubled.

The Register described the breakthrough as essentially doubling memory density and the number of dies obtainable from a wafer. CXMT’s published figure supports an increase of at least 50%, not a demonstrated doubling. The distinction is substantial: a 50% increase corresponds to 1.5 times the previous count, while doubling means twice the count.

The same report described the products as having 24GB of memory. CXMT specifies 24Gb—gigabits—per die. With eight bits to a byte, that is equivalent to 3GB per die, not a 24GB memory module. The announcement identifies two package formats, 496-ball and 245-ball, but does not describe them as 24GB modules.

For manufacturing economics, gross die count is another important qualifier. It measures the potential number of dies before accounting for how many pass production testing. More dies per wafer could improve output and cost competitiveness, but the gain in usable chips depends on manufacturing yield. CXMT does not disclose yield figures in this announcement.

The process changes behind G5​

CXMT attributes the platform’s improvements to several manufacturing changes rather than a single breakthrough. Its published process metrics include:

  • Quadruple patterning, identified as SAQP, enables an active-area half-pitch of 11.95 nanometers in the memory arrays.
  • Process-flow changes and new material integration bring the array capacitor aspect ratio to 45:1.
  • A DRAM-optimized high-k metal-gate process reduces the reported core cell-array height to 6,762 nanometers.

These are measurements of particular structures within the manufacturing process. The 11.95nm half-pitch figure should therefore retain that description; treating it as a universal “11.95nm chip” designation would discard the measurement’s actual scope.

CXMT says these capabilities rival the industry’s best mass-produced nodes. Its announcement supplies physical process metrics, however, rather than a comparative evaluation of finished products from CXMT, Samsung, SK Hynix and Micron. It does not establish equivalent performance, production yields or reliability across those suppliers’ portfolios.

The company also describes a digital-twin platform spanning design, tape-out, manufacturing and yield maintenance, using DRAM process models to accelerate development. That is part of its account of how G5 was developed, not a disclosed measurement of production output or cost savings.

What buyers can—and cannot—conclude​

CXMT says both new LPDDR5X products are already in mass production. This places the announcement beyond a laboratory demonstration or a future manufacturing roadmap, although the company has not disclosed shipment volumes, pricing or named customers for these products. Their stated target is smartphones and portable consumer electronics; no Windows-system adoption is identified.

The useful implication is conditional but straightforward: if CXMT can sustain acceptable yields, fitting more dies onto each wafer could strengthen its cost position and increase the amount of usable memory it produces. Higher per-die capacity could also give device manufacturers additional memory-packaging options. Neither consequence establishes a particular retail price.

For PC buyers and IT procurement teams, this is a manufacturing milestone to watch rather than a reason to postpone a purchase. The announcement documents a new production platform and mobile-memory products; a purchasing decision would require evidence of adoption in specific systems, actual availability and pricing. Those steps remain separate from CXMT’s claimed process advance.