Intel Nova Lake ES1 Reportedly Used 18A-P Before TSMC N2P Compute Tile Shift

What was reported​

Wccftech's report relies on posts by the hardware leaker Jaykihn from October 17 and 18, 2026. The ES1 samples reportedly had a compute tile in an 8+16 configuration on 18A-P: eight Coyote Cove P-cores and sixteen Arctic Wolf E-cores.

The leaker's account is a Q&A. Intel designed the 8+16 tile for both nodes. The 18A-P version was used for ES1 sampling that would not have existed with N2P, because N2P's timeline was later. The 18A-P 8+16 design was reportedly intended for ES1 only.

The other reported details:

• ES1 samples on 18A-P were made in April and May, according to Wccftech. ES2 samples on N2P followed in July and August.
• Wccftech says Nova Lake qualification samples are already out.
• The 18A-P tiles reportedly used backside power delivery (BSPDN), which Wccftech links to clock gains.
• Early samples let partners get the HX 28-core die sooner than N2P would have allowed.

None of this has been confirmed by Intel. The dates, the sample stages and the node sequence all rest on the leaker.

Why a sample can use a different node​

The idea is simple even if the engineering isn't. Early engineering samples let motherboard makers, OEMs and software teams start validating while the final silicon is still being finished. If the final node isn't ready yet, a stand-in on another node can keep the schedule moving.

Intel's design rules make this plausible. In its June 2026 VLSI announcement, Intel said 18A-P is fully design rule compatible with 18A, which makes it easy to reuse existing IP and design flows. That says nothing about how easily a design moves from 18A-P to TSMC. Porting a CPU tile between foundries is a separate piece of work, and the leaker says Intel did the design twice.

For buyers, the practical point is that early benchmark leaks may not match retail silicon. An ES1 chip on 18A-P could behave differently from an N2P part in clocks, power and thermals. Nova Lake leaks should be read with that in mind.

What the public record supports​

Several details can be checked against official material, even though the sample story cannot.

Intel 18A-P. Intel said on June 16, 2026 that 18A-P, the first performance enhancement in the 18A family, had entered risk production. Intel claims it delivers 9% higher performance at the same power, or 18% lower power at the same performance, compared with 18A. It also introduced a "Power Boost" transistor option aimed at higher frequency. That announcement doesn't mention Nova Lake.

Backside power. Intel's VLSI talk quantified the benefit of backside power delivery. It cited up to a 6% frequency uplift, or more than 15% lower dynamic power, versus a comparable frontside design. That fits Wccftech's mention of clock gains in general terms. It doesn't show that the Nova Lake ES1 samples reached any particular clock speed.

TSMC N2P. TSMC's technology page says N2 entered volume production in 2025. It describes N2P as giving a 5% performance uplift while keeping N2's design rules. Those are foundry-level claims. They don't compare directly with Intel 18A-P, and they don't test the "unsuitable" label.

Other reporting on the node split​

Other outlets have reported on the Nova Lake node mix recently, and the picture is mixed.

• On October 16, 2026, TweakTown reported leaked Nova Lake-H and HX die shots from Moore's Law Is Dead. They showed a compute tile hosting up to 8P+16E cores on TSMC N2P, spanning 104mm². The SoC and peripheral control tiles were reportedly on Intel 18A-P. That is also leak-sourced, but it matches the idea that the final compute tile is at TSMC.
• In July, TrendForce summarized a KeyBanc-sourced report that 80–90% of Nova Lake compute tiles might now be made in-house. That would contradict an all-N2P compute tile. It was also a rumor, and it predates the latest leaks.

So the reported sourcing is inconsistent. The N2P compute tile has the most support in the latest leaks, but the volume split between Intel and TSMC is unsettled.

Where to be skeptical​

• Single source. Wccftech's account is built on a handful of posts. Jaykihn's claims may well be accurate, but they are unverified.
• The "unsuitable" claim. Wccftech says 18A-P's performance and density were "unsuitable" against N2P and that this may explain the switch. That is the outlet's interpretation. The leaker's stated reason is timing. No benchmarks or Intel statements back a node-quality verdict, so it shouldn't be read as Intel judging its own process inferior.
• Product scope. The report doesn't say Intel is abandoning 18A-P. Reports place other Nova Lake tiles on 18A-P, and Intel has presented 18A-P as a real product node.
• Roadmap items. The leaker also said the cancelled Beast Lake was evaluated on N2/P and 18A-P, and that Panther Lake-S was 18A only. Those are unconfirmed.
• Table figures. Wccftech's comparison table shows a 52-core maximum and a 2027 launch. These are leak-derived and shouldn't be treated as specifications.

What to do with this​

If you build or buy PCs, don't treat early-sample performance or power leaks as final numbers. Wait for retail silicon and independent reviews. If you manage hardware purchasing, plan around Intel's official launch announcements and platform documentation, not sample rumors.

The strongest verified takeaway is narrow: 18A-P is a real node in risk production with published gains, and TSMC N2P is a mature node. Whether Nova Lake's first samples used 18A-P rests on one leaker. Intel hasn't commented.