Speaking at the "Semiconductors Powering Humanoids" conference at COEX in Seoul on October 16, 2026, Intel Vice President Cho Min-sung outlined the company's multi-year physical AI and robotics system-on-chip (SoC) trajectory. According to South Korean electronics industry publication THE ELEC, Cho confirmed that Intel plans to introduce its next-generation Nova Lake architecture for physical AI applications in early 2027, followed by Razor Lake-AX in 2028.
What does a 700-TOPS robotics chip mean for the broader x86 ecosystem, edge computing, and the PC builders watching from the sidelines? Let's unpack the actual numbers, separate confirmed roadmap targets from persistent silicon rumors, and look at why physical AI is suddenly driving heavy-duty processor design.
The Seoul Roadmap Disclosure: From Panther Lake to Razor Lake-AX
The core news comes directly from Cho's remarks in Seoul, first reported by THE ELEC and subsequently covered by VideoCardz, Digital Trends, eTeknix, TechPowerUp, and Technetbook. Addressing how edge processors dictate the real-time capabilities of autonomous machines, Cho contrasted Intel’s current robotics hardware with what is coming over the next two years.
Currently, Intel's robotics development tools based on the Panther Lake architecture—marketed as the Core Ultra Series 3 platform—theoretically deliver up to 180 TOPS of combined AI performance across the central processing unit (CPU), neural processing unit (NPU), and graphics processing unit (GPU).
"We plan to introduce the next-generation Nova Lake early next year, followed by Razor Lake AX in 2028, targeting performance of around 700 TOPS," Cho stated at the conference, as quoted by THE ELEC.
If you do the back-of-the-napkin math, jumping from Panther Lake's theoretical 180 TOPS to a 700-TOPS target represents a 3.88x increase—nearly quadrupling the raw theoretical AI compute ceiling in roughly two years.
| Platform Generation | Target Release Window (Robotics) | Stated Peak AI Compute Target | Primary Confirmed Scope |
|---|---|---|---|
| Panther Lake (Core Ultra Series 3) | Current | Up to 180 TOPS (theoretical combined) | Industrial robotic arms, AMRs, humanoids, edge/PC |
| Nova Lake | Early 2027 | Not specified in Seoul remarks | Next-generation physical AI and robotics bridge |
| Razor Lake-AX | 2028 | ~700 TOPS (roadmap target) | Autonomous mobile robots and humanoid systems |
Summary of the Roadmap Shift
- Current Baseline: Panther Lake (Core Ultra Series 3) provides up to 180 theoretical TOPS for edge and robotics dev kits.
- The 2027 Bridge: Nova Lake arrives in early 2027 to serve the initial wave of commercial autonomous mobile robots (AMRs).
- The 2028 Heavyweight: Razor Lake-AX is slated for 2028, aiming for roughly 700 TOPS to coincide with customer timelines for humanoid robot mass production.
Why 700 TOPS Needs a Grain of Salt (and a Spec Sheet)
In the modern semiconductor industry, TOPS has become the favorite marketing megaphone for every chipmaker on the planet. Whether we are talking about Windows 11 Copilot+ PCs requiring a 40-TOPS NPU or edge servers crunching vision models, bigger numbers always look better on a presentation slide. However, veteran system architects and hardware analysts know that a raw TOPS figure without context is like bragging about a car's engine RPM without mentioning the transmission or the fuel type.
As Digital Trends and VideoCardz rightly point out, Intel’s 700-TOPS figure is currently a high-level roadmap target rather than a validated, shipping specification. More importantly, the Seoul disclosure omitted several critical technical parameters:
- Numerical Precision and Sparsity: We do not yet know what data type Intel is using to calculate that 700 TOPS. Is it INT8, FP8, or heavily quantized FP4 with sparsity enabled? Halving the bit-width of an operation often doubles the theoretical TOPS count on paper without necessarily doubling real-world throughput on complex models.
- Compute Split (CPU vs. GPU vs. NPU): On Panther Lake, the 180 TOPS figure is a combined metric pooling the CPU, GPU, and NPU. Intel has not disclosed how much of Razor Lake-AX’s 700 TOPS will come from a dedicated neural engine versus an oversized integrated GPU.
- Power Envelope and Thermals: A chip pulling 700 TOPS at 35 watts is a miracle of silicon engineering; a chip pulling 700 TOPS at 180 watts is a portable space heater. Neither TDP nor memory bandwidth was confirmed during the presentation.
The Nvidia Comparison Trap
To put the 700-TOPS target into perspective, THE ELEC contrasted Razor Lake-AX with Nvidia’s Jetson AGX Orin, a widely deployed robotics SoC that delivers roughly 275 TOPS. Against Orin, 700 TOPS looks like a massive 2.5x generational leap.
However, Nvidia has not been sitting on its hands waiting for 2028. As eTeknix and VideoCardz note, Nvidia has already showcased its next-generation Jetson Thor robotics platform, which claims up to 2,070 TFLOPS of sparse FP4 AI compute. Comparing Intel's unspecified 700 TOPS directly against Nvidia's sparse FP4 TFLOPS is an apples-to-oranges exercise. Until Intel publishes a formal architecture brief detailing the data types, memory subsystem, and sustained performance per watt, we cannot definitively rank these platforms in practical robotic workloads.
What Happened to the "Strix Halo Killer" PC Rumors?
If you frequent hardware forums, "Razor Lake-AX" probably caught your eye for a very different reason than factory robots. Prior to this conference, the "-AX" suffix surfaced in hardware leaks and diagnostic tool updates alongside rumors of a monstrous enthusiast APU.
According to earlier leaks summarized by VideoCardz, Digital Trends, and eTeknix, the "-AX" variant was rumored to pack either 16 or 32 Xe3P graphics cores, paired with a wide memory interface and potentially even on-package memory. That hypothetical spec sheet looked tailor-made to challenge AMD’s Ryzen AI Max (Strix Halo) chips in ultra-thin gaming notebooks, mini-PCs, and local LLM workstations without requiring a discrete GPU.
Does Intel pitching Razor Lake-AX at a humanoid robotics conference mean the high-end PC dream is dead? Not necessarily, though a healthy dose of realism is required:
- Rumors vs. Confirmations: The 16-to-32 Xe3P core counts and on-package memory details remain unconfirmed leaks. Intel did not verify internal silicon layouts in Seoul.
- Shared Silicon Economics: Designing a bespoke, giant monolithic or multi-tile SoC solely for humanoid robots in 2028 would be an expensive gamble. In the x86 world, edge and robotics platforms regularly share foundational silicon with client and workstation processors. After all, Intel’s current robotics platform is built directly on Panther Lake (Core Ultra Series 3), which is first and foremost a mobile PC architecture.
- The Unanswered PC Question: While Intel has not confirmed whether Razor Lake-AX will ever land in consumer laptops or mini-PCs, a processor capable of pushing 700 TOPS of local AI inference without a discrete graphics card would be just as attractive to a Windows power user running local vision-language models as it is to a robotics engineer.
For now, however, PC enthusiasts should treat Razor Lake-AX as an confirmed edge and robotics SoC first, and an unconfirmed consumer APU second.
Why Humanoid Robots Need Local x86 Muscle
Why is Intel—and the wider semiconductor industry—suddenly obsessed with "Physical AI"? Unlike a cloud-hosted chatbot that can afford a 500-millisecond network round-trip to a data center when generating an email, a bipedal humanoid robot or a fast-moving warehouse AMR operates in the unforgiving world of gravity and human coworkers.
If a robot relies on cloud connectivity to analyze camera feeds, identify an obstacle, calculate balance adjustments, and actuate its motors, a brief Wi-Fi drop doesn't just cause a buffering spinner—it causes a two-hundred-pound machine to tip over. Perception, decision-making, and action must happen entirely on-device in real time.
According to Cho's presentation in Seoul, Intel’s domestic partners in South Korea are planning to begin mass production of autonomous mobile robots in 2027, while most are targeting 2028 for full humanoid deployments. That customer timeline is the exact reason Intel sequenced Nova Lake for early 2027 and aligned Razor Lake-AX for 2028.
Intel's Hardware and Software Robotics Stack
Silicon alone doesn't move robotic joints; developers need a cohesive software and hardware harness to deploy models without rewriting low-level code for every sensor. Alongside the chip roadmap, THE ELEC highlighted how Intel is positioning its ecosystem around these processors:
- Robinson Bay: Intel's integrated hardware and software development platform, built to let engineering teams prototype and deploy complete robotic systems directly on Core Ultra Series 3 hardware.
- OpenVINO: Intel’s established AI toolkit designed to optimize model inference specifically for edge environments where compute and power budgets are tightly constrained.
- Physical AI Studio: A comprehensive development suite tailored for building and training robotics AI workflows.
- Robotics AI Suite: Software focused on deterministic, real-time robot control to ensure precise and safe physical operation.
By pairing familiar x86 compatibility and OpenVINO optimization with a promise of 700 TOPS down the road, Intel is trying to convince robotics firms to build their 2026 prototypes on Panther Lake today, migrate to Nova Lake in 2027, and drop Razor Lake-AX into their humanoid production lines in 2028 without abandoning their software stack.
Key Takeaways for IT Pros and Hardware Watchers
- Razor Lake-AX is Official: After months of diagnostic leaks, Intel has publicly confirmed the Razor Lake-AX name and set a 2028 launch window.
- Nova Lake Leads in 2027: Before Razor Lake-AX arrives, Nova Lake will serve as Intel's early-2027 step for physical AI and autonomous mobile robots.
- Wait for the Architecture Brief: The ~700 TOPS figure is nearly four times Panther Lake's 180 TOPS, but until Intel discloses numerical precision, power draw, and whether those rumours of massive Xe3P integrated graphics are true, treat the number as an early roadmap target rather than a benchmark.