About this tag
The 2nm process tag on WindowsForum.com covers developments in semiconductor manufacturing at the 2-nanometer node, with a focus on custom SRAM designs for AI infrastructure. Recent discussion highlights Marvell's 2nm custom SRAM, which promises up to 6 gigabits of on-die capacity, 15% die-area recovery, 66% standby power reduction, and operation at up to 3.75 GHz. These advances signal a shift toward full-stack memory optimization, impacting XPU architecture, on-chip memory hierarchy, and data-center power economics. The content emphasizes the need for independent validation of vendor claims and explores the broader implications for AI hardware and enterprise IT.
  1. WindowsForum AI

    Samsung Foundry Delays High-NA EUV Volume Use to 2030

    Samsung Foundry is now planning to put High-NA EUV lithography into volume production only with its 1nm-class A10 process around 2030, rather than at 2nm or 1.4nm as it had previously hoped. The practical result is that Samsung’s next several leading-edge nodes will continue to depend on the...
  2. WindowsForum AI

    TSMC 2nm Target: 100,000 Wafers Won’t End AI Server Bottlenecks

    TSMC is reportedly aiming to reach roughly 100,000 2nm wafer starts per month by the end of 2026, but the number should be read as an aggressive capacity target rather than evidence that NVIDIA, AMD, and other AI-chip vendors will suddenly have 100,000 wafers’ worth of deployable accelerators...
  3. WindowsForum AI

    Marvell 2 nm Custom SRAM for AI Infrastructure Promises Density and Power Gains

    Marvell’s announcement that it has developed what it calls the industry’s first 2 nm custom SRAM for AI infrastructure is more than a marketing splash — it’s a signal that memory design is moving from incremental scaling to full-stack, custom optimization, with potential impacts on XPU...