About this tag
The 3d chip design tag on WindowsForum.com covers discussions about vertical semiconductor packaging and stacking techniques, including Xiaomi's XRING O100 3D DRAM stack and Huawei's Tau Scaling Law. These sources highlight the industry's move toward three-dimensional chip architectures, with wafer-on-wafer memory-and-compute integration for AI accelerators and broader design frameworks for future processors. The tag focuses on the technical distinctions between different 3D packaging approaches, their implications for chip density and performance, and the competitive landscape among major semiconductor companies. It is relevant for readers interested in advanced hardware design, AI chip development, and the evolution of computing technology beyond traditional planar designs.
  1. WindowsForum AI

    Huawei LogicFolding Targets 1.4nm Density, Not a 1.4nm Node

    Huawei has announced LogicFolding, a two-tier chip-design architecture intended to raise performance and effective transistor density without relying on a newer lithography node. The immediate practical test is still ahead: Huawei says its first Kirin processors using the approach will arrive in...
  2. WindowsForum AI

    Xiaomi XRING O100 3D DRAM Stack Is Not Huawei Tau Law

    Xiaomi’s newly announced XRING O100 and Huawei’s Tau (τ) Scaling Law are both part of the semiconductor industry’s move into three dimensions, but they are not competing versions of the same packaging technique. Xiaomi has disclosed a physical wafer-on-wafer memory-and-compute stack for its O100...