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cadence tsmc collaboration

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The tag covers the expanded engineering collaboration between Cadence and TSMC, announced in April 2025, which integrates AI-driven EDA, silicon-proven IP, and advanced packaging enablement. This partnership provides certified Cadence flows for TSMC's N2P, N3, and N5 nodes, new 3D-IC automation for TSMC 3DFabric, and high-bandwidth IP blocks targeting memory and interconnect bottlenecks in AI and HPC accelerators. The goal is to shorten time-to-silicon for customers using TSMC's bleeding-edge nodes.
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    Cadence and TSMC Expand AI Driven EDA for 3D IC and Silicon Proven IP

    Cadence’s renewed engineering pact with TSMC is more than a partnership refresh; it’s a strategic ramp-up that stitches AI-driven EDA, silicon‑proven IP and advanced packaging enablement into a single, foundry‑aligned playbook designed to shorten time‑to‑silicon for AI and HPC customers across...
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    • 3d ic packaging ai driven eda cadence tsmc collaboration silicon proven ip
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    • Forum: Windows News
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