Number of Memory Devices: 2 Total Physical Memory: 2047 MB (0 MB) Total Available Physical Memory: 1169 MB Memory Load: 42%
[TABLE]
[TR]
[/TR]
[TR]
[TD="class: value"]Ram Type[/TD]
[TD="class: altvalue"]DDR2[/TD]
[TD="class: altvalue"]DDR2[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Standard Name[/TD]
[TD="class: altvalue"]DDR2-800[/TD]
[TD="class: altvalue"]DDR2-800[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Module Name[/TD]
[TD="class: altvalue"]PC2-6400[/TD]
[TD="class: altvalue"]PC2-6400[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"]Memory Capacity (MB)[/TD]
[TD="class: altvalue"]1024[/TD]
[TD="class: altvalue"]1024[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"]Bus Clockspeed (Mhz)[/TD]
[TD="class: altvalue"]400.00[/TD]
[TD="class: altvalue"]400.00[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"]Jedec Manufacture Name[/TD]
[TD="class: altvalue"]Transcend Information[/TD]
[TD="class: altvalue"]Transcend Information[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"]Search Amazon.com[/TD]
[TD="class: altvalue"]Search![/TD]
[TD="class: altvalue"]Search![/TD]
[/TR]
[TR]
[TD="class: value, width: 240"]SPD Revision[/TD]
[TD="class: altvalue"]1.2[/TD]
[TD="class: altvalue"]1.2[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"]Registered[/TD]
[TD="class: altvalue"]No[/TD]
[TD="class: altvalue"]No[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"]ECC[/TD]
[TD="class: altvalue"]No[/TD]
[TD="class: altvalue"]No[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"]DIMM Slot #[/TD]
[TD="class: altvalue"]1[/TD]
[TD="class: altvalue"]2[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"]Manufactured[/TD]
[TD="class: altvalue"]Year 2000[/TD]
[TD="class: altvalue"]Year 2000[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"]Module Part #[/TD]
[TD="class: altvalue"]JM388Q643A-8[/TD]
[TD="class: altvalue"]JM388Q643A-8[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"]Module Revision[/TD]
[TD="class: altvalue"]0x0[/TD]
[TD="class: altvalue"]0x0[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"]Module Serial #[/TD]
[TD="class: altvalue"]0x0[/TD]
[TD="class: altvalue"]0x0[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"]Module Manufacturing Location[/TD]
[TD="class: altvalue"]84[/TD]
[TD="class: altvalue"]84[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"]# of Row Addressing Bits[/TD]
[TD="class: altvalue"]14[/TD]
[TD="class: altvalue"]14[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"]# of Column Addressing Bits[/TD]
[TD="class: altvalue"]10[/TD]
[TD="class: altvalue"]10[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"]# of Banks[/TD]
[TD="class: altvalue"]4[/TD]
[TD="class: altvalue"]4[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"]# of Ranks[/TD]
[TD="class: altvalue"]2[/TD]
[TD="class: altvalue"]2[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"]Device Width in Bits[/TD]
[TD="class: altvalue"]8[/TD]
[TD="class: altvalue"]8[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"]Bus Width in Bits[/TD]
[TD="class: altvalue"]64[/TD]
[TD="class: altvalue"]64[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"]Module Voltage[/TD]
[TD="class: altvalue"]SSTL 1.8V[/TD]
[TD="class: altvalue"]SSTL 1.8V[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"]CAS Latencies Supported[/TD]
[TD="class: altvalue"]3 4 5[/TD]
[TD="class: altvalue"]3 4 5[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"]Timings @ Max Frequency[/TD]
[TD="class: altvalue"]5-5-5-18[/TD]
[TD="class: altvalue"]5-5-5-18[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Minimum Clock Cycle Time, tCK (ns)[/TD]
[TD="class: altvalue"]2.500[/TD]
[TD="class: altvalue"]2.500[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Minimum CAS Latency Time, tAA (ns)[/TD]
[TD="class: altvalue"]12.500[/TD]
[TD="class: altvalue"]12.500[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Minimum RAS to CAS Delay, tRCD (ns)[/TD]
[TD="class: altvalue"]12.500[/TD]
[TD="class: altvalue"]12.500[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Minimum Row Precharge Time, tRP (ns)[/TD]
[TD="class: altvalue"]12.500[/TD]
[TD="class: altvalue"]12.500[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Minimum Active to Precharge Time, tRAS (ns)[/TD]
[TD="class: altvalue"]45.000[/TD]
[TD="class: altvalue"]45.000[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Minimum Row Active to Row Active Delay, tRRD (ns)[/TD]
[TD="class: altvalue"]7.500[/TD]
[TD="class: altvalue"]7.500[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Minimum Auto-Refresh to Active/Auto-Refresh Time, tRC (ns)[/TD]
[TD="class: altvalue"]57.500[/TD]
[TD="class: altvalue"]57.500[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Minimum Auto-Refresh to Active/Auto-Refresh Command Period, tRFC (ns)[/TD]
[TD="class: altvalue"]105.500[/TD]
[TD="class: altvalue"]105.500[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"][/TD]
[TD="class: altvalue"][/TD]
[TD="class: altvalue"][/TD]
[/TR]
[TR]
[TD="class: value, width: 240"]DDR2 Specific SPD Attributes[/TD]
[TD="class: altvalue"][/TD]
[TD="class: altvalue"][/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Data Access Time from Clock, tAC (ns)[/TD]
[TD="class: altvalue"]0.400[/TD]
[TD="class: altvalue"]0.400[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Clock Cycle Time at Medium CAS Latency (ns)[/TD]
[TD="class: altvalue"]3.750[/TD]
[TD="class: altvalue"]3.750[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Data Access Time at Medium CAS Latency (ns)[/TD]
[TD="class: altvalue"]0.500[/TD]
[TD="class: altvalue"]0.500[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Clock Cycle Time at Short CAS Latency (ns)[/TD]
[TD="class: altvalue"]5.000[/TD]
[TD="class: altvalue"]5.000[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Data Access Time at Short CAS Latency (ns)[/TD]
[TD="class: altvalue"]0.600[/TD]
[TD="class: altvalue"]0.600[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Maximum Clock Cycle Time (ns)[/TD]
[TD="class: altvalue"]8.000[/TD]
[TD="class: altvalue"]8.000[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Write Recover Time, tWR (ns)[/TD]
[TD="class: altvalue"]15.000[/TD]
[TD="class: altvalue"]15.000[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Internal Write to Read Command Delay, tWTR (ns)[/TD]
[TD="class: altvalue"]7.500[/TD]
[TD="class: altvalue"]7.500[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Internal Read to Precharge Command Delay, tRTP (ns)[/TD]
[TD="class: altvalue"]7.500[/TD]
[TD="class: altvalue"]7.500[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Address/Command Setup Time Before Clock, tIS (ns)[/TD]
[TD="class: altvalue"]0.170[/TD]
[TD="class: altvalue"]0.170[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Address/Command Hold Time After Clock, tIH (ns)[/TD]
[TD="class: altvalue"]0.250[/TD]
[TD="class: altvalue"]0.250[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Data Input Setup Time Before Strobe, tDS (ns)[/TD]
[TD="class: altvalue"]0.050[/TD]
[TD="class: altvalue"]0.050[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Data Input Hold Time After Strobe, tDH (ns)[/TD]
[TD="class: altvalue"]0.120[/TD]
[TD="class: altvalue"]0.120[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Maximum Skew Between DQS and DQ Signals (ns)[/TD]
[TD="class: altvalue"]0.200[/TD]
[TD="class: altvalue"]0.200[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Maximum Read Data hold Skew Factor (ns)[/TD]
[TD="class: altvalue"]0.240[/TD]
[TD="class: altvalue"]0.240[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] PLL Relock Time (ns)[/TD]
[TD="class: altvalue"]0.000[/TD]
[TD="class: altvalue"]0.000[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] DRAM Package Type[/TD]
[TD="class: altvalue"]Planar[/TD]
[TD="class: altvalue"]Planar[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Burst Lengths Supported[/TD]
[TD="class: altvalue"]4 8[/TD]
[TD="class: altvalue"]4 8[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Refresh Rate[/TD]
[TD="class: altvalue"]Reduced (7.8us)[/TD]
[TD="class: altvalue"]Reduced (7.8us)[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] # of PLLS on DIMM[/TD]
[TD="class: altvalue"]0[/TD]
[TD="class: altvalue"]0[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] FET Switch External Enable[/TD]
[TD="class: altvalue"]No[/TD]
[TD="class: altvalue"]No[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Analysis Probe Installed[/TD]
[TD="class: altvalue"]No[/TD]
[TD="class: altvalue"]No[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Weak Driver Supported[/TD]
[TD="class: altvalue"]Yes[/TD]
[TD="class: altvalue"]Yes[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] 50 Ohm ODT Supported[/TD]
[TD="class: altvalue"]Yes[/TD]
[TD="class: altvalue"]Yes[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Partial Array Self Refresh Supported[/TD]
[TD="class: altvalue"]Yes[/TD]
[TD="class: altvalue"]Yes[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Module Type[/TD]
[TD="class: altvalue"]UDIMM[/TD]
[TD="class: altvalue"]UDIMM[/TD]
[/TR]
[TR]
[TD="class: value, width: 240"] Module Height (mm)[/TD]
[TD="class: altvalue"]30.0[/TD]
[TD="class: altvalue"]30.0[/TD]
[/TR]
[/TABLE]