Tom’s Hardware reports that an 8P+12E+4 LP-E Nova Lake part would retain 36MB of L3 cache—the same reported amount as the 8P+16E+4 version—rather than fall to the previously rumored 33MB. It also says a 4P+4E+4 LP-E part would retain 18MB, matching the 4P+8E+4 model instead of dropping to 15MB.
Those two revisions are significant only if Intel ships the configurations as described. They suggest that disabling an E-core cluster does not necessarily mean Intel disables the associated L3 cache slice. For buyers, that could make lower-core-count parts more attractive in cache-sensitive games and workloads than their core counts alone would imply.
Intel has not announced Nova Lake desktop or HX processors, their cache structure, the reported bLLC variants, or any of the specific SKUs in this leak. The numbers remain a roadmap rumor, not a specification sheet.
The report changes the assumed link between E-cores and L3 cache
Nova Lake’s rumored core notation needs unpacking before the cache claims can be useful. In the 8P+12E+4 LP-E example, the first number refers to performance cores, the second to main efficiency cores, and the final four reportedly refers to low-power E-cores. The central claim is not that Intel has added cache to the chip after the fact; it is that a physically present cache resource might stay enabled even where one main E-core cluster is disabled.
Earlier Nova Lake cache reporting, including analysis by ComputerBase, described a design in which cache capacity could be associated with groups of P-cores and E-core clusters. That made a proportional cut intuitive: remove four E-cores, remove the cache slice linked to that cluster. Jaykihn’s August 12 update, relayed by Tom’s Hardware, instead says the 8P+12E+4 and 4P+4E+4 parts would keep the cache capacity of their fully enabled counterparts.
If accurate, this would be a familiar sort of product binning rather than an architectural miracle. Semiconductor vendors routinely sell partially disabled versions of a larger die. A defect or commercial segmentation decision can turn off execution cores while leaving other functional blocks active. Cache retention can improve the practical value of a cut-down chip, especially when a workload is more constrained by cache capacity or memory latency than by peak multicore throughput.
The important limitation is that the leak does not establish a rule that all disabled Nova Lake E-core clusters retain their cache. It identifies two reported exceptions.
The 6P+12E+4 entry is internally inconsistent
Tom’s Hardware’s article contains a conflict that should prevent readers from treating its entire revised table as settled. The embedded Jaykihn update says “lower SKUs are unaffected” and gives 6P+12E+4 as still having 30MB. Yet the article’s prose says the 6P+12E+4 configuration is limited to 27MB rather than 30MB, and its own comparison table also lists 27MB.
Those are not interchangeable figures. A 3MB gap is exactly the size of the purported change in the 8P+12E+4 example, so it changes the interpretation of whether 6P+12E+4 is a normal lower-tier design, a cache-reduced bin, or another configuration with retained cache.
Until Jaykihn clarifies the discrepancy—or Intel publishes technical documentation—the only defensible reading is narrow:
- Tom’s Hardware reports revised 36MB and 18MB L3 figures for the 8P+12E+4 and 4P+4E+4 configurations.
- The report does not provide a consistent L3 figure for the 6P+12E+4 configuration.
- No independently reported correction or Intel confirmation was available for the August 12 claim.
That discrepancy matters more than it may first appear. The 6P+12E+4 model is also said to be one of the configurations that could receive Intel’s rumored big last-level cache, or bLLC, option. A muddled base-L3 number makes it harder to understand what buyers would actually receive before that additional cache is considered.
Base L3 and bLLC should not be added casually
The report lists 132MB of bLLC for the alleged 8P+12E+4 chip and 108MB for the purported 6P+12E+4 model. These figures are presented separately from ordinary L3 cache. That distinction is essential, because online discussion has increasingly treated Nova Lake’s rumored cache capacity as a single headline total.
According to the leak, the 8P+12E+4 part would have 36MB of ordinary L3 plus 132MB of bLLC, while a 6P+12E+4 bLLC variant would pair its disputed 27MB-or-30MB base figure with 108MB of additional cache. The reported 144MB and 132MB bLLC capacities are not confirmation that every processor carrying those core counts will include large cache. Tom’s Hardware says non-bLLC variants of the single-tile designs are also expected.
That creates at least two possible purchasing tiers for the same broad core layout: a conventional-cache part and a bLLC-equipped part. The latter could be Intel’s attempt to compete in the workload categories where AMD’s 3D V-Cache Ryzen chips have built a strong reputation, particularly gaming at settings where the CPU and memory subsystem, rather than the graphics card, set the frame-rate ceiling.
But bLLC should not yet be described as Intel’s equivalent of 3D V-Cache in any technical sense. The report calls it a challenge to AMD’s technology, while prior Nova Lake coverage has suggested a different packaging and cache-layout approach. Capacity alone does not reveal cache latency, bandwidth, power behavior, clock trade-offs, software behavior, or price. Those details will decide whether the comparison is meaningful.
The retained-cache theory has practical limits
A retained L3 slice could benefit cut-down Nova Lake models in a few specific situations: large game working sets, compilation tasks with repeatedly accessed code and data, and applications whose performance deteriorates once data spills from cache into main memory. It would not turn a 12-E-core chip into a 16-E-core chip. Heavily threaded rendering, encoding, virtualization, and other sustained parallel workloads still benefit from the missing execution resources.
Nor does a larger L3 number guarantee a visible gain. Cache-sensitive software varies sharply by engine, data set, memory configuration, operating system scheduling, and the mix of P-cores, E-cores, and LP-E cores actually available to a task. Windows users should be particularly wary of making buying decisions based on a leak’s cache total before independent benchmarks test thread scheduling and real application behavior.
The clue worth watching is whether Intel positions these parts with different model suffixes, cache branding, or price bands. If a 24-core 8P+12E+4 processor truly carries the same 36MB base L3 as a 28-core 8P+16E+4 chip, Intel could create a lower-priced SKU that loses less gaming performance than its disabled E-core cluster would normally suggest. If the full cache is merely a byproduct of harvesting a larger die, availability could also be constrained by yields rather than planned as a permanent feature.
What prospective Nova Lake buyers should do now
There is no action for existing Windows PC owners beyond separating the rumor from the roadmap. Nova Lake remains unannounced, and the report itself demonstrates why early SKU tables should be treated as provisional: a single update changed two cache estimates and introduced—or revealed—an unresolved conflict around another.
The useful takeaway is narrower. Watch for confirmation of the 8P+12E+4 and 4P+4E+4 cache allocations, and do not assume that fewer E-cores automatically means less L3 cache on Nova Lake. At the same time, do not use the reported 6P+12E+4 figure in comparison charts until the 27MB-versus-30MB contradiction is resolved.
If Intel eventually ships these bins, the retained-cache models could complicate the usual “more cores equals better SKU” ladder. Until Intel publishes the product stack and reviewers can test it, the 36MB and 18MB figures are best treated as an interesting binning clue—not a reason to delay a PC purchase or to forecast performance from a cache total alone.
