This is a semiconductor-economics story, not a PC product story. Nothing announced changes the DDR5 or LPDDR modules you can buy or upgrade today. The webinar did not announce any consumer-facing price, capacity or availability change. It does show how Micron expects the DRAM in future PCs, laptops and servers to get denser and cheaper per bit.
What 4F² and 6F² actually mean
DRAM cell sizes are written as multiples of F², where F is the minimum lithographic feature size. SK hynix describes 4F² as a cell occupying a 2F by 2F area. The same SK hynix description notes that 6F² cells are the common design today. The idealized arithmetic is simple. A 4F² cell is one-third smaller than a 6F² cell. If footprint were the only constraint, you could fit about 50% more cells in the same area.
That is the "holy grail" appeal. More bits per wafer should mean lower cost per bit, or more capacity per chip without a smaller process node. But the 50% figure is a theoretical ceiling. A real die also has capacitors, peripheral circuitry and manufacturing limits.
Micron's argument
DeBoer's central claim is that the cell label is not what sets DRAM bit density. In the webinar transcript, he said the capacitor pitch and the capacitor size and dimensions set the density. Underneath, designers can arrange the transistors as 6F² or 4F² to fit a given capacitor pitch. In his framing, the real job is optimizing process complexity, margin and cost around that capacitor pitch.
He made three further points:
- It can be built. DeBoer acknowledged that 4F² can be built a few nodes back. He called it more complicated and more costly, but said there was "no question" it can be done.
- Scaling is the problem. He said Micron sees 4F² as lacking a viable scaling path beyond a certain point. In his words, there are fundamental problems with 4F² scaling. He did not name the specific physical mechanism.
- 3D DRAM is the endpoint. He said those problems ultimately lead to 3D DRAM taking over instead of 4F².
These are DeBoer's and Micron's technical judgments. They are not a settled industry finding, and the transcript offers no independent test data.
Micron's roadmap instead
Micron plans to keep scaling conventional 6F² planar DRAM for several more nodes.
- 1γ (1-gamma): Micron says it is in high-volume manufacturing and was the node where it introduced EUV.
- 1δ (1-delta): Micron says it intends to ramp it in volume in the second half of 2027, with a mid-20s percentage bit-density improvement. It said the node is optimized for AI products, including HBM.
- Later nodes: Micron described pathfinding on 1ζ and further nodes. These combine High-NA EUV, new materials and other innovations. It also described a node that uses wafer bonding.
- 3D DRAM: Micron says it is on the roadmap as a parallel path. Reports on the webinar slides place it between the 1ζ and 1η nodes. DeBoer said timing will depend on cost, complexity and device performance. No commercial date was given, so it should not be read as imminent.
DeBoer also said DRAM is nearing atomic limits, though Micron has confidence in several more planar nodes. For comparison, the same webinar said Micron's next NAND generation (Gen11) is also due in the second half of 2027.
A split with the competition
Micron's position is a divergence from its rivals. SK hynix publicly laid out a 30-year roadmap at IEEE VLSI in June 2025. It said it would apply a 4F² vertical-gate platform and 3D DRAM to nodes at the 10-nanometer level or below. Tom's Hardware, citing TechInsights, reports that Samsung and SK hynix both still carry 4F² cells in their roadmaps. I could not verify the company-specific detail behind that claim, because the TechInsights roadmap is subscription material and I could not read it.
China's CXMT adds pressure. Reports say CXMT recently announced intentions to commercialize 4F² server DRAM, and memory stocks fell on the news. Futunn reports the webinar was partly meant to address investor concerns raised by CXMT's earlier disclosure. That context matters. A company defending its roadmap to investors has an incentive to present its own path as the sensible one.
There is precedent for Micron going its own way. Tom's Hardware notes that Micron delayed adopting EUV lithography while its rivals moved earlier, and still stayed competitive on cost and performance. As the webinar transcript tells it, Micron then introduced EUV at 1γ. That history makes the 4F² decision less surprising. It does not prove Micron is right this time.
What this means for PC and IT readers
- Near term: nothing changes. This is about nodes arriving in 2027 and later.
- Long term: it suggests the industry may split over how to get denser DRAM, with Micron on 6F² then 3D, and SK hynix on 4F² vertical gate plus 3D. If one approach proves cheaper, the cost per gigabyte of future memory could favor that vendor.
- Competing claims: each vendor's roadmap is a projection. The winner will show up in yields, cost and shipping products, not in conference slides.
Bottom line: Micron says capacitor pitch, not cell footprint, is what limits DRAM density. It is skipping 4F² and betting on 6F² scaling followed by 3D DRAM. Samsung and SK hynix may be betting the other way, and the next several DRAM generations will show who was right.