TechPowerUp first reported the arrangement on September 14, saying the companies have been working on a bridge built from organic materials, fine copper wiring, and redistribution layers rather than Intel-style silicon bridges. Separate reporting carried by ChainCatcher describes the work as more than a year into development and reliability evaluation. Neither Samsung Electro-Mechanics nor Qualcomm has publicly announced a production agreement, a product name, launch window, volume commitment, or performance result.
The distinction is important because the initial report calls the work a Samsung Foundry manufacturing effort. The available record points instead to Samsung Electro-Mechanics, Samsung’s package-substrate business, as the company developing and producing the substrate samples. Samsung Foundry may participate in package evaluations, but it is not interchangeable with the substrate supplier—and calling this a new Qualcomm wafer-foundry win would overstate what has been reported.
An organic bridge aims to avoid a full silicon interposer
Advanced chips increasingly combine separate dies—compute tiles, I/O dies, cache, networking blocks, and memory interfaces—in one package. The hard part is connecting those dies with enough bandwidth and low enough power use to make them operate like one processor, without creating an enormous and costly monolithic chip.
Intel’s Embedded Multi-die Interconnect Bridge, or EMIB, is one established answer. EMIB places small silicon bridges only where adjacent dies need dense connections, avoiding a full silicon interposer beneath the complete package. That can reduce silicon area relative to a conventional 2.5D package, though it retains the manufacturing complexity of embedding and assembling very thin silicon pieces inside an organic package substrate.
The Samsung Electro-Mechanics approach described by TechPowerUp uses an organic bridge instead. In practical terms, the bridge is a small, localized high-density wiring structure made with organic dielectric materials and copper routing, embedded in a cavity within an FC-BGA substrate. The bridge would sit beneath the edges of neighboring dies and provide their shortest, densest electrical paths, while the rest of the package uses less demanding substrate wiring.
That architecture is why the “2.1D” label is used. It occupies the middle ground between ordinary organic package substrates and 2.5D designs using a broad silicon interposer. The term is not a universal industry standard, and vendors apply 2.xD labels inconsistently, but Samsung Electro-Mechanics has publicly used 2.1D to describe substrates that connect dies directly without a silicon interposer.
Samsung Electro-Mechanics showed 2.1D package-substrate technology at KPCA Show 2026 in Incheon on September 9 through 11. Its own announcement said the technology enables direct chip-to-chip connection without a silicon interposer, aimed at the high-density connections required in AI semiconductor packages. The company did not identify Qualcomm in that announcement.
The reported numbers are ambitious, but they are targets rather than product specifications
According to TechPowerUp and the parallel ChainCatcher report, the proposed bridge would use roughly five to seven redistribution layers, with line-and-space dimensions targeted at 1.5 to 2 micrometers, vias of 4 to 5 micrometers, and a die-to-die pattern density of 500 to 1,000 connections per millimeter. Those are not minor refinements to a conventional server motherboard or ordinary package substrate; they place the bridge in the ultra-fine-pitch territory necessary for high-bandwidth chiplet links.
Samsung Foundry’s public advanced-packaging material provides useful context, though it describes a related 2.3D RDL-interposer technology rather than this Qualcomm-specific project. Samsung says its 2.3D Cube-R organic RDL interposer is being developed at 2/2-micrometer line and space, positioning organic redistribution-layer packaging as a lower-cost alternative to a silicon bridge solution. In other words, the reported dimensions are technically aligned with the direction Samsung’s semiconductor businesses have already laid out publicly.
But targets are not shipping capability. The missing evidence includes electrical loss measurements, signaling speeds, power delivery, thermal behavior, bridge yield, substrate warpage data, reliability test results, and the package size that Samsung Electro-Mechanics can build repeatably. Those omissions matter more than the headline geometry, especially for large AI accelerators where thermal cycling and mechanical stress can break a promising package long before its wiring density becomes commercially useful.
Organic materials introduce a familiar engineering trade-off. They can be processed using manufacturing methods closer to advanced substrate and PCB production, potentially lowering cost and improving scalability versus a large silicon interposer. They also expand and contract differently from silicon under temperature changes, and fine copper routes, microvias, and die-edge connections must survive both fabrication and years of operation under heavy data-center loads.
The industry has been trying to solve those problems for years. Samsung Electro-Mechanics has patents covering bridge-embedded substrates, while Qualcomm’s own recruiting materials published this year explicitly listed organic bridges, RDL-like substrates, and 2D chiplet product introduction among the responsibilities for a package engineering role in South Korea. Those records support the broader proposition that both sides are investing in this packaging category. They do not confirm a commercial Qualcomm accelerator built with Samsung’s bridge.
Qualcomm’s data-center roadmap is the potential customer, not a confirmed product
TechPowerUp reported that Qualcomm could apply the technology to a multi-die AI accelerator, with several compute dies connected on a common package substrate. That makes strategic sense: Qualcomm has been expanding its data-center ambitions beyond its traditional mobile-chip business, and multi-die packaging is central to building large accelerators without betting the entire design on one giant die.
A bridge-based substrate could let Qualcomm partition an accelerator into smaller dies and reserve the most expensive interconnect density for the boundaries that need it. That potentially improves manufacturing economics because a defect ruins a smaller die rather than a giant monolithic chip. It also allows a designer to mix process nodes or reuse an I/O die across products, though the packaging design becomes more difficult and the die-to-die interface must be engineered as carefully as the chips themselves.
For Windows and enterprise IT readers, this remains an upstream infrastructure story rather than a reason to expect a new AI PC part. Qualcomm’s current Windows-on-Arm platforms use tightly integrated mobile-style system-on-chips; no evidence ties the reported organic bridge to a future Snapdragon X device. The reported target is instead multi-chip AI hardware for data centers, where package cost, accelerator scale, and memory connectivity increasingly determine what systems enterprises can deploy.
Samsung Electro-Mechanics also said other customers are evaluating its 2.1D direction, although it named none of them. That is unsurprising: package substrates have become a bottleneck technology for AI servers as chips add more compute dies, high-bandwidth memory, and higher I/O counts. The commercially relevant question is whether Samsung can qualify this bridge at scale before customers decide they need silicon bridges, large RDL interposers, or full 3D stacking instead.
Samsung’s opportunity is in substrates, not a declared Qualcomm foundry comeback
The story lands amid continuing uncertainty over Qualcomm’s use of Samsung’s leading-edge logic manufacturing. Recent reporting from The Bell, republished by Investing.com, said Samsung and Qualcomm had delayed negotiations around a possible 2-nanometer application-processor contract over pricing. That is separate from the organic bridge project, but it underscores why the supplier identity matters.
A package-substrate deal can be meaningful even if Qualcomm does not award Samsung Foundry a major wafer contract. Samsung Electro-Mechanics makes the FC-BGA substrate; Samsung Foundry develops chip packaging services and can provide assembly or integration input; Qualcomm remains the fabless customer designing the dies. Those roles can overlap within the Samsung corporate group, but they are commercially and technically different businesses.
For now, the defensible conclusion is narrower than the “alliance” framing suggests: Qualcomm and Samsung Electro-Mechanics appear to be evaluating an organic-bridge 2.1D substrate for future multi-die chips, while Samsung’s public materials confirm that it is advancing 2.1D and organic-RDL packaging more broadly. Until either company discloses a qualified product, a package platform, or a volume-production date, the development is a credible packaging bet—not a confirmed accelerator launch or a renewed Qualcomm foundry contract.