Microwire’s argument that Nvidia’s CUDA position is being dismantled by custom AI chips, Chinese open models and domestic lithography points to real shifts in the market. But its central conclusion is ahead of the evidence. CUDA is losing exclusivity in selected workloads, not losing relevance across AI computing, and the most consequential Chinese hardware claim in the piece remains a small-scale, early production report rather than proof of an independent high-end accelerator supply chain.
The distinction matters for Windows developers, enterprise AI teams and infrastructure buyers deciding whether to standardize on Nvidia hardware, test alternatives, or place bets on a supposedly post-GPU stack. The practical answer is to keep reducing single-vendor dependencies at the framework and model layer while treating Nvidia as the default high-performance platform for the foreseeable deployment cycle.
Nvidia’s own latest financial results make the market position clear. It reported $62.3 billion in Data Center revenue for the quarter ended January 25, 2026, a 75% increase from a year earlier, and forecast $78 billion in total revenue for the following quarter despite assuming no Data Center compute revenue from China. That is not the profile of a platform already displaced. It is evidence that customers continue to buy an integrated package of accelerators, networking, systems, libraries and operational support at enormous scale.
The strongest part of Microwire’s case is the rise of application-specific accelerators. Google TPU, AWS Trainium and Inferentia, Meta’s MTIA, and Microsoft’s Maia family are all real attempts to move particular AI workloads away from general-purpose GPUs.
Google describes TPU as a custom accelerator used across training and inference, including its own frontier-model infrastructure. AWS has positioned Trainium for training and Inferentia for inference. Meta has said that its MTIA program is built around its ranking, recommendation and generative-AI workloads, while Microsoft designed Maia for Azure’s large-scale AI services. The vendors are pursuing these chips because a hyperscaler with predictable workloads can lower operating costs by owning the silicon, racks, networking and software path.
But this is vertical integration, not broad hardware interchangeability. A cloud provider’s internal accelerator is useful only when its toolchain, capacity, instance availability and model support fit the customer’s workload. Organizations using an Azure service backed by Maia or a Google-managed TPU cluster have not gained a portable replacement for CUDA hardware in their own datacenter. They have accepted a different form of provider dependence.
The same constraint applies to on-premises deployments. Nvidia’s advantage is not merely that CUDA exists; it is that enterprises can buy hardware from many server vendors, run mature driver stacks, use familiar frameworks and find extensive support across inference servers, observability tools, storage suppliers and networking partners. A proprietary cloud ASIC can pressure Nvidia’s margins and reduce GPU demand at the largest buyers without giving a typical enterprise an equivalent alternative.
For IT teams, the immediate implication is straightforward: assess custom silicon through the cloud service that exposes it, not as a universal GPU substitute. Validate pricing, regional capacity, framework support, model portability and egress terms before treating an accelerator discount as a strategic escape from lock-in.
Triton is particularly relevant because it is an open-source language and compiler intended to let developers write efficient deep-learning primitives at a higher level than CUDA. Its current project supports Nvidia GPUs and AMD’s ROCm stack, with Ascend-oriented work being developed separately through Triton-Ascend. That is meaningful progress: a kernel developer can increasingly target an intermediate programming model rather than maintain entirely separate CUDA and ROCm implementations.
Yet it would be a mistake to equate abstraction with hardware neutrality. Triton’s own compatibility material still exposes different back ends and device-specific capabilities. Production performance depends on compiler maturity, supported data types, collective communications, memory behavior, kernel libraries and debugging tools. Code can become more portable without delivering the same performance or operational predictability on every accelerator.
Microwire also describes Triton as “OpenAI’s Triton.” OpenAI originated the project, but the relevant present-day fact is that Triton is maintained in the public triton-lang project. More importantly, it is not a generic switch that turns any AI chip into a CUDA-equivalent target. It is one component in a stack whose back ends continue to require substantial vendor work.
This is where the CUDA moat is genuinely being tested. The high-level framework layer increasingly gives users a choice, and the growing ability to compile or adapt workloads for alternatives lowers switching costs. The moat has not vanished, because the difficult work starts below the Python model definition.
That is a consequential move for the Ascend ecosystem. Open code makes it easier for Chinese developers, server makers and software vendors to inspect interfaces, contribute operators, package environments and improve framework support without waiting for a closed vendor SDK. Huawei’s PyTorch extension,
CANN is still not an open, chip-neutral acceleration standard in the way Microwire implies. It remains software designed around Huawei’s Ascend NPUs. Open-sourcing the stack can reduce Huawei’s own software bottleneck and invite ecosystem participation; it does not automatically make CANN a common layer for Cambricon, Hygon and every other domestic accelerator vendor.
Microwire says those vendors are “coalescing” around open acceleration frameworks, but provides no public compatibility matrix, joint release, benchmark suite or production deployment evidence to establish that claim. The available record supports a more measured conclusion: Huawei is opening the Ascend stack at a time when Chinese AI developers need alternatives to restricted U.S. hardware and software dependencies. Whether competitors adopt CANN as a shared base remains unproven.
DeepSeek’s V3 technical report substantiates the architectural point. Its model uses a mixture-of-experts design with 671 billion total parameters but activates 37 billion per token, and it uses Multi-head Latent Attention to improve efficiency. Those choices can reduce the computation and memory burden of serving models, particularly when compared with a dense model of similar total size.
What they do not establish is a break from Nvidia hardware. DeepSeek’s own report said V3 training used 2.788 million H800 GPU-hours. Efficient algorithms lower the required compute per useful output; they can also make Nvidia clusters more productive. An efficiency breakthrough is not automatically a competitive defeat for the hardware vendor whose accelerators trained the model.
Qwen’s source code is available under Apache 2.0, and many Qwen model releases have permissive terms. But the claim that Qwen alone has produced “hundreds of thousands” of downstream fine-tunes is not backed by a cited methodology in Microwire’s article. Model downloads, repository forks, quantizations, instruction-tuned variants and commercial deployments are different measurements. The larger conclusion—that open weights are spreading rapidly—holds without relying on an unsupported number.
For enterprise teams, open-weight models create leverage. They enable local inference, data-residency controls, model customization and the ability to use a mix of Nvidia, AMD, cloud accelerators or CPU-based deployments. They do not eliminate the need to qualify the runtime and hardware combination that will carry the production load.
If confirmed at scale, that is an important development. Immersion DUV tools are among the most difficult pieces of the semiconductor manufacturing chain to localize, and domestic production would reduce China’s exposure to foreign equipment restrictions. DUV with multi-patterning can also be used to make more advanced chips than its nominal single-exposure resolution suggests.
The reporting does not support Microwire’s portrayal of a fully ramped domestic lithography route for high-density AI accelerators. The reported volumes are small, the initial capability and yield remain unclear, and multi-patterning carries process complexity, cost and overlay challenges compared with EUV production. Reuters’ account was itself based on The Information’ reporting; no public technical validation of the claimed tools’ commercial performance was available in the record reviewed here.
Export controls have unquestionably pushed Chinese firms to invest more aggressively in domestic alternatives. They have not yet demonstrated that sanctions produced a complete AI hardware decoupling. Nvidia’s forecast excluding China revenue, the continuing importance of H800-class training hardware in published Chinese-model research, and the limited reported DUV output all point to a market in transition rather than one that has already separated.
The GPU monoculture is under pressure from custom silicon, open-weight models and improving software portability. But buyers should read the present situation as a diversification opportunity, not a completed transfer of power. The next procurement decisions will still be made workload by workload: model framework, inference latency, training scale, deployment location, supportability and total cost—not by a declaration that CUDA has already fallen.
Nvidia’s own latest financial results make the market position clear. It reported $62.3 billion in Data Center revenue for the quarter ended January 25, 2026, a 75% increase from a year earlier, and forecast $78 billion in total revenue for the following quarter despite assuming no Data Center compute revenue from China. That is not the profile of a platform already displaced. It is evidence that customers continue to buy an integrated package of accelerators, networking, systems, libraries and operational support at enormous scale.
Custom silicon is changing cloud economics
The strongest part of Microwire’s case is the rise of application-specific accelerators. Google TPU, AWS Trainium and Inferentia, Meta’s MTIA, and Microsoft’s Maia family are all real attempts to move particular AI workloads away from general-purpose GPUs.Google describes TPU as a custom accelerator used across training and inference, including its own frontier-model infrastructure. AWS has positioned Trainium for training and Inferentia for inference. Meta has said that its MTIA program is built around its ranking, recommendation and generative-AI workloads, while Microsoft designed Maia for Azure’s large-scale AI services. The vendors are pursuing these chips because a hyperscaler with predictable workloads can lower operating costs by owning the silicon, racks, networking and software path.
But this is vertical integration, not broad hardware interchangeability. A cloud provider’s internal accelerator is useful only when its toolchain, capacity, instance availability and model support fit the customer’s workload. Organizations using an Azure service backed by Maia or a Google-managed TPU cluster have not gained a portable replacement for CUDA hardware in their own datacenter. They have accepted a different form of provider dependence.
The same constraint applies to on-premises deployments. Nvidia’s advantage is not merely that CUDA exists; it is that enterprises can buy hardware from many server vendors, run mature driver stacks, use familiar frameworks and find extensive support across inference servers, observability tools, storage suppliers and networking partners. A proprietary cloud ASIC can pressure Nvidia’s margins and reduce GPU demand at the largest buyers without giving a typical enterprise an equivalent alternative.
For IT teams, the immediate implication is straightforward: assess custom silicon through the cloud service that exposes it, not as a universal GPU substitute. Validate pricing, regional capacity, framework support, model portability and egress terms before treating an accelerator discount as a strategic escape from lock-in.
Open frameworks weaken low-level dependence, but do not erase it
Microwire correctly identifies PyTorch, JAX and Triton as important abstraction layers. Most machine-learning engineers write model code and tensor operations rather than hand-author CUDA kernels. That creates room for accelerators from Nvidia, AMD, Google, AWS and Huawei to compete for framework support.Triton is particularly relevant because it is an open-source language and compiler intended to let developers write efficient deep-learning primitives at a higher level than CUDA. Its current project supports Nvidia GPUs and AMD’s ROCm stack, with Ascend-oriented work being developed separately through Triton-Ascend. That is meaningful progress: a kernel developer can increasingly target an intermediate programming model rather than maintain entirely separate CUDA and ROCm implementations.
Yet it would be a mistake to equate abstraction with hardware neutrality. Triton’s own compatibility material still exposes different back ends and device-specific capabilities. Production performance depends on compiler maturity, supported data types, collective communications, memory behavior, kernel libraries and debugging tools. Code can become more portable without delivering the same performance or operational predictability on every accelerator.
Microwire also describes Triton as “OpenAI’s Triton.” OpenAI originated the project, but the relevant present-day fact is that Triton is maintained in the public triton-lang project. More importantly, it is not a generic switch that turns any AI chip into a CUDA-equivalent target. It is one component in a stack whose back ends continue to require substantial vendor work.
This is where the CUDA moat is genuinely being tested. The high-level framework layer increasingly gives users a choice, and the growing ability to compile or adapt workloads for alternatives lowers switching costs. The moat has not vanished, because the difficult work starts below the Python model definition.
Huawei’s CANN move is real, but its scope is narrower than the claim
Huawei announced in August 2025 that it would fully open-source CANN, its Ascend hardware enablement layer, along with parts of the Mind application and tooling stack. The company subsequently described plans to release core components including operators, domain libraries, graph-engine technology, Ascend C and MindIE. Public Ascend repositories also include PyTorch integration, CANN container materials and the Triton-Ascend project.That is a consequential move for the Ascend ecosystem. Open code makes it easier for Chinese developers, server makers and software vendors to inspect interfaces, contribute operators, package environments and improve framework support without waiting for a closed vendor SDK. Huawei’s PyTorch extension,
torch_npu, gives teams another path to migrate existing PyTorch workloads to Ascend processors.CANN is still not an open, chip-neutral acceleration standard in the way Microwire implies. It remains software designed around Huawei’s Ascend NPUs. Open-sourcing the stack can reduce Huawei’s own software bottleneck and invite ecosystem participation; it does not automatically make CANN a common layer for Cambricon, Hygon and every other domestic accelerator vendor.
Microwire says those vendors are “coalescing” around open acceleration frameworks, but provides no public compatibility matrix, joint release, benchmark suite or production deployment evidence to establish that claim. The available record supports a more measured conclusion: Huawei is opening the Ascend stack at a time when Chinese AI developers need alternatives to restricted U.S. hardware and software dependencies. Whether competitors adopt CANN as a shared base remains unproven.
China’s open-weight models are a distribution advantage, not a hardware escape
The report is also right that Chinese labs have become important suppliers of open-weight models. Alibaba’s Qwen family, DeepSeek, Zhipu GLM and Moonshot AI’s Kimi have expanded the set of models enterprises can run, fine-tune and host themselves rather than obtain only through a U.S. cloud API.DeepSeek’s V3 technical report substantiates the architectural point. Its model uses a mixture-of-experts design with 671 billion total parameters but activates 37 billion per token, and it uses Multi-head Latent Attention to improve efficiency. Those choices can reduce the computation and memory burden of serving models, particularly when compared with a dense model of similar total size.
What they do not establish is a break from Nvidia hardware. DeepSeek’s own report said V3 training used 2.788 million H800 GPU-hours. Efficient algorithms lower the required compute per useful output; they can also make Nvidia clusters more productive. An efficiency breakthrough is not automatically a competitive defeat for the hardware vendor whose accelerators trained the model.
Qwen’s source code is available under Apache 2.0, and many Qwen model releases have permissive terms. But the claim that Qwen alone has produced “hundreds of thousands” of downstream fine-tunes is not backed by a cited methodology in Microwire’s article. Model downloads, repository forks, quantizations, instruction-tuned variants and commercial deployments are different measurements. The larger conclusion—that open weights are spreading rapidly—holds without relying on an unsupported number.
For enterprise teams, open-weight models create leverage. They enable local inference, data-residency controls, model customization and the ability to use a mix of Nvidia, AMD, cloud accelerators or CPU-based deployments. They do not eliminate the need to qualify the runtime and hardware combination that will carry the production load.
Domestic DUV is strategically important, but it is not a mature replacement for ASML
The newest part of the story is its reference to domestic Chinese immersion DUV lithography. Reuters reported on July 27, citing The Information, that China had begun manufacturing domestically developed immersion deep-ultraviolet systems. The report said output would initially be about five machines in 2026 and roughly 20 in 2027.If confirmed at scale, that is an important development. Immersion DUV tools are among the most difficult pieces of the semiconductor manufacturing chain to localize, and domestic production would reduce China’s exposure to foreign equipment restrictions. DUV with multi-patterning can also be used to make more advanced chips than its nominal single-exposure resolution suggests.
The reporting does not support Microwire’s portrayal of a fully ramped domestic lithography route for high-density AI accelerators. The reported volumes are small, the initial capability and yield remain unclear, and multi-patterning carries process complexity, cost and overlay challenges compared with EUV production. Reuters’ account was itself based on The Information’ reporting; no public technical validation of the claimed tools’ commercial performance was available in the record reviewed here.
Export controls have unquestionably pushed Chinese firms to invest more aggressively in domestic alternatives. They have not yet demonstrated that sanctions produced a complete AI hardware decoupling. Nvidia’s forecast excluding China revenue, the continuing importance of H800-class training hardware in published Chinese-model research, and the limited reported DUV output all point to a market in transition rather than one that has already separated.
The GPU monoculture is under pressure from custom silicon, open-weight models and improving software portability. But buyers should read the present situation as a diversification opportunity, not a completed transfer of power. The next procurement decisions will still be made workload by workload: model framework, inference latency, training scale, deployment location, supportability and total cost—not by a declaration that CUDA has already fallen.
References
- Primary source: microwire.info
Published: 2026-08-01T14:06:42+00:00
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