DigiTimes first reported the revised insertion point, and Tom’s Hardware separately detailed comments from Chang Min Park, Samsung Electronics’ Master VP of Technology, at the 2026 Next-Generation Lithography + Patterning Conference. Park said Samsung had wanted High-NA EUV in mass production for 2nm and 1.4nm, but that the technology still needs more improvement. Samsung’s stated threshold is now A10 and smaller.
This is a meaningful correction to the way Samsung’s roadmap has sometimes been read. Samsung has not abandoned 1.4nm: its first-quarter 2026 earnings material still says the node is “on track,” while reporting around the company’s revised foundry roadmap places SF1.4 volume production in 2029. What has moved is the use of High-NA equipment, not necessarily the entire 1.4nm program.
Samsung’s roadmap has slowed where it matters most
Samsung publicly committed in 2022 to mass production of a 2nm process in 2025 and a 1.4nm process in 2027. Four years later, the 1.4nm target has shifted to 2029, while the company’s near-term emphasis is a much broader SF2 family: mobile-oriented variants, high-performance versions, automotive processes and a 2nm node with backside power delivery.
That two-year slide is significant on its own. A foundry does not make its money by being first to announce a node; it makes its money when customers can tape out chips, the process delivers predictable yields, and the fab can produce enough wafers at an acceptable cost. Samsung’s current position suggests that it sees more commercial value in making 2nm a durable platform than in forcing a new lithography generation into an immature 1.4nm launch.
The revised plan also separates two issues that were being conflated. SF1.4 is Samsung’s next process designation, expected in 2029. A10 is its future 1nm-class process, expected around 2030. The labels do not describe a literal one-nanometer-wide transistor feature; modern node names are process-generation brands. Still, the sequence matters: Samsung now intends to make 1.4nm chips without High-NA EUV before introducing the new scanner technology with A10.
For PC and server buyers, this means no immediate change to products. Samsung’s 2nm and 1.4nm wafers may eventually reach smartphone processors, AI accelerators, networking silicon and other high-performance designs, but a 2030 lithography insertion is many product cycles away. The nearer consequence falls on Samsung’s ability to offer foundry customers a credible alternative to TSMC and Intel in the late 2020s.
Why High-NA EUV is not a plug-in upgrade
High-NA EUV is ASML’s next-generation extreme-ultraviolet platform, raising the numerical aperture of the optics from 0.33 to 0.55. In simple terms, the larger aperture improves image resolution on the wafer. ASML says its EXE systems can print 8nm-resolution features and reduce some layers from multiple exposures to a single exposure.
That promise is why High-NA was once treated as an obvious successor for the smallest logic nodes. Fewer patterning steps can reduce cycle time, process complexity and opportunities for defects. In a mature production flow, that can improve both economics and yield.
But the word mature is doing the work here. The new optics bring their own manufacturing compromises. ASML’s anamorphic design cuts the exposure field in half compared with current NXE EUV scanners. That can complicate large-chip layout and raises the prospect of stitching adjacent exposures for some designs. The platform also requires changes beyond the scanner itself: masks, pellicles, photoresists, metrology, inspection, computational lithography and defect control all have to perform together at production scale.
Samsung’s decision therefore should not be read as a declaration that High-NA EUV has failed. It is an acknowledgement that a sharper image alone does not make a profitable chip process. The company has a High-NA scanner for research, according to Tom’s Hardware, but laboratory learning and volume output are fundamentally different milestones.
Samsung is choosing to extract more life from its existing EUV fleet. Standard 0.33-NA EUV can still reach tighter geometries through multi-patterning, in which a layer is exposed and processed in more than one pass. The trade-off is extra masks, more process steps, longer cycle times and more opportunities for overlay errors. Yet those costs may be preferable to committing early to a new scanner architecture and its incomplete production supply chain.
The gap between ASML’s promise and Samsung’s schedule
ASML has positioned High-NA EUV as a platform for high-volume logic manufacturing from 2025–2026 and says it can support future nodes beginning at 2nm. Samsung’s new timeline shows why equipment roadmaps and foundry roadmaps cannot be treated as interchangeable.
A scanner vendor can qualify a machine for shipment and process development well before every customer has determined that the machine is economical for its own design rules, mask infrastructure and product mix. Samsung appears to be making exactly that distinction. It is not saying 2nm cannot be made with High-NA EUV; it is saying that Samsung does not presently see a persuasive production case for it at 2nm or 1.4nm.
The company’s internal benchmark is telling. Park’s reported comment that High-NA becomes “necessary” from A10 onward implies Samsung believes conventional EUV methods can still meet its 2nm and 1.4nm requirements. The word necessary is more revealing than a generic promise of future adoption: it frames High-NA as a tool to be deployed when current EUV can no longer meet the desired combination of density, yield and cost.
This is also a reminder that lithography choices are not a simple race to buy the newest machine. Intel has been more aggressive in public about High-NA development and its future 14A-class process, while TSMC has taken a more conservative approach. TSMC’s published 2026 plans put A14 volume production in 2028, but do not commit that node to High-NA EUV. Samsung is now visibly closer to that cautious camp than to an early-adopter strategy.
A 2nm execution bet, not a retreat from leading-edge foundry
Samsung’s public financial materials give the broader business context. The company says it is ramping second-generation 2nm mobile products, pursuing larger 2nm customer engagements, and sees its advanced-node lines running at full utilization. Its 1.4nm program remains on the roadmap, but Samsung’s immediate commercial task is turning the SF2 family into a process customers will trust for large designs.
That is particularly important because Samsung’s foundry division has spent years trying to improve customer confidence in advanced-node yields and capacity. A leading process name has limited value if a chip designer cannot secure wafers, hit power targets consistently or scale from an initial tape-out into millions of units. Retaining proven EUV tooling for the next two generations may constrain some theoretical scaling gains, but it reduces the number of variables Samsung must stabilize at once.
The old 2022 roadmap promised rapid progression: 2nm in 2025, 1.4nm in 2027. The updated plan is slower, but it is more explicit about what comes between those milestones. Samsung is building out 2nm derivatives first, then SF1.4 in 2029, then A10 with High-NA EUV around 2030. That sequence gives customers a clearer indication that the company is prioritizing an extended process family rather than a series of one-off node announcements.
There is a limit to what can be concluded from the announcement. Samsung has not published a detailed A10 design-rule document, a list of High-NA layers, target yields, customer commitments, expected wafer pricing or a volume-capacity forecast. It has also not said whether its first A10 customers will be internal Samsung designs, external mobile clients, AI-chip companies or automotive suppliers. Those omissions matter because High-NA’s economic case can vary sharply by die size and product type.
What Samsung has actually delayed
The concrete delay is High-NA EUV in volume manufacturing, not access to the technology, not research activity, and not Samsung’s entire 1.4nm effort. Samsung has already been working with the equipment, and its next nodes can still use conventional EUV. The revised roadmap says the company will wait until A10 before turning High-NA into a production dependency.
For Windows PC enthusiasts, the move is less about a chip arriving late in a laptop and more about who can credibly manufacture future CPUs, GPUs and AI accelerators. Samsung is betting that dependable 2nm and 1.4nm production will matter more to prospective customers than being the first foundry to put High-NA EUV on a volume line.
By 2030, Samsung’s A10 launch will be the real test of that bet. Until then, the company has chosen a narrower and more practical goal: make the 2nm platform sellable at scale, bring SF1.4 to production in 2029, and avoid letting an unfinished lithography transition become the weak point in either node.