DigiTimes reported the research direction on September 17, with an account carried by Industry Events describing a GAA development path that does not depend on extreme-ultraviolet lithography as its core technology. Tom’s Hardware subsequently detailed the functional-device results and the missing measurements that prevent a commercial-node comparison. The available coverage traces the announcement to DigiTimes rather than an independently reproduced experiment.
What IMECAS has demonstrated
According to Tom’s Hardware, citing DigiTimes, Ye Tianchun, chief engineer of China’s National Major Special Project 02, told the IC World conference in Beijing that IMECAS had completed “early process integration” for stacked nanosheet-channel GAA transistors fabricated using DUV lithography.
That is a meaningful device-development milestone. A gate-all-around transistor places the controlling gate around its channel—the region through which current flows. Tom’s Hardware explains that this arrangement provides better electrostatic control as transistor dimensions shrink, which is why GAA structures are important to advanced semiconductor development.
The architecture and the lithography method address different parts of the problem. GAA describes the transistor’s structure; DUV describes the patterning technology used in fabrication. Demonstrating that researchers can combine them into functional devices establishes a research route, while leaving open how densely those devices can be packed and whether the process can support complete chips.
Tom’s Hardware reports two on/off current ratios, written as Ion/Ioff, of 9.7 × 10⁵ and 7.6 × 10⁵. These correspond to approximately 970,000:1 and 760,000:1, respectively, and exceed the cited 500,000:1 benchmark.
Those ratios describe the separation between conducting and non-conducting states. They support the conclusion that the gate can control current in the experimental structures. They do not, by themselves, establish switching speed, processor power consumption, transistor density or manufacturing yield.
Why “3nm” remains a target
The most consequential omission is device geometry. According to Tom’s Hardware, IMECAS has not disclosed gate pitch, metal pitch, nanosheet dimensions, transistor density or SRAM density.
Each would answer a different question about whether this research could become a competitive manufacturing technology:
- Gate and metal pitches would help establish how tightly transistor structures and wiring can be arranged.
- Nanosheet dimensions would put the demonstrated channel structures into a physical scaling context.
- Transistor density would help show how much logic could fit into a given area.
- SRAM density would help assess the memory structures needed alongside logic in a practical processor.
Without those measurements, an electrical switching result cannot establish equivalence to a commercial 3nm-class node. The “3nm” designation describes the intended development direction, rather than a demonstrated density or product-performance level.
This also limits comparisons with other chipmakers. A working GAA structure is evidence of architectural progress, but the shared use of GAA does not make two manufacturing processes equivalent. The reported current ratios cannot fill the missing geometry and integration data.
From individual devices to a manufacturing process
Tom’s Hardware distinguishes IMECAS’s experimental transistor flow from even a defined flow for producing research chips. Commercial production would require considerably broader integration.
Lithography must work with deposition, etching, cleaning, materials, temperature limits, metrology and process control. Those operations must collectively produce usable devices and connections repeatedly—not merely demonstrate that a transistor structure can function.
The practical implication is that two separate advances remain to be established: sufficiently scaled devices, and a complete process capable of building chips reliably. Publishing competitive transistor dimensions would strengthen the first case, but would not automatically prove the second.
The strategic attraction is clear. Chinese chipmakers without access to EUV scanners have an incentive to investigate advanced transistor structures using DUV equipment. IMECAS’s reported result gives that effort a concrete experimental basis. It does not establish independence from every other restricted manufacturing technology, or demonstrate production economics.
For PC buyers and enterprise hardware planners, this announcement offers no supported basis for expecting a particular processor, availability date or performance gain. Its significance is upstream: researchers have reportedly made functional devices along a potentially useful EUV-free development path. A complete 3nm-class manufacturing process remains undemonstrated, and the disclosed evidence does not support a timetable for one.