Micron Memory Roadmap: No 4F² DRAM, Custom HBM and G11 NAND Production Targeted for 2027

Micron held a technology webinar on October 21, 2026. Scott DeBoer, its president and chief technology and products officer, presented the DRAM, HBM and NAND roadmaps and took analyst questions. Tom's Hardware's Anton Shilov later published a detailed breakdown of the plans. StorageReview added NAND-specific context.

This article covers company targets and plans, not shipping products. Only two items have a firm production window: 1δ DRAM and G11 NAND, both in the second half of 2027. Everything else is development work.

DRAM: Micron skips 4F² and keeps scaling with 6F²​

The most surprising decision is what Micron left out. Shilov reports that Micron dropped plans for 4F² DRAM cells, which CXMT, Samsung and SK hynix are pursuing. Micron's stated reason is that it sees no viable scaling path beyond where it is today. Micron is extending 6F² and will not build 4F².

Whether that is brave or risky is an open question. It is Micron's own technical judgment, not an industry consensus. Rivals may succeed with 4F², or they may hit problems Micron says it foresaw.

The node ladder​

• 1γ (1-gamma): This node is in high-volume manufacturing. It is Micron's first DRAM node to use EUV lithography. Earlier nodes used DUV multipatterning.
• 1δ (1-delta): This node is in yield ramp and slated for mass production in the second half of 2027. Micron expects bit density to rise by a mid-20% figure over 1γ. Micron plans to make it in the U.S. It is intended for DDR, LPDDR, graphics memory, HBM5, vertical HBM and vertical edge inference memory.
• 1ε (1-epsilon): This node introduces wafer bonding. Micron has not said which structures it will bond, what the gains will be, or when it will ship. Futurum's summary puts wafer bonding at 1ε and 3D DRAM on the route after 1δ in 2H 2027.
• ζÅ (zeta-angstrom): This node is in early development and brings High-NA EUV to Micron's memory. Tom's Hardware notes that Samsung and SK hynix plan High-NA at their DRAM fabs in 2028. It judges that Micron's node is unlikely before 2030, which is the publication's own inference. Micron gave no date.
• ηÅ (eta-angstrom): This node is at the pathfinding stage. Micron mentions new materials but hasn't named them. Tom's Hardware's list of candidates, such as photoresists and dielectrics, is speculation.

3D DRAM and CMOS​

Micron is developing two generations of 3D DRAM, called 3D1 and 3D2. It will introduce them when cost and performance beat planar DRAM. It has disclosed no layer counts, density targets or dates. DeBoer's framing was that DRAM is nearing atomic limits, but he expressed confidence in several more planar nodes.

Micron also expects the performance of its DRAM peripheral CMOS logic to rise more than 10x between 2020 and 2030. That path runs through high-k metal gate logic and then 3D CMOS. It is a company projection, not a measured result.

Custom HBM and vertical memory​

The theme in the headline, custom silicon, shows up most clearly in HBM. Starting with HBM4E, Micron will offer standard and custom versions. Custom HBM5E, vertical HBM (vHBM) and vertical edge inference memory (vEIM) follow.

• Custom base dies: Customers can shrink the memory I/O width or add logic to the HBM base die. DeBoer said this logic is often an offload from GPU circuitry. The idea is to free compute-die area and tune power and performance.
• Foundry processes: Micron will use advanced foundry processes for the base dies. It has named no nodes. It expects HBM4E to need more advanced CMOS.
• vHBM: This stacks memory directly on top of ASICs and CPUs instead of beside them on an interposer. The promise is higher bandwidth and lower latency. The cost is power delivery and heat. Micron points to hybrid bonding, integrated heat spreaders and thermally aware design. It expects conventional HBM and vHBM to coexist, with vHBM for peak bandwidth and HBM for capacity.
• vEIM: This targets power efficiency over raw bandwidth. The first generation aims for 2 TB/s at under 1 picojoule per bit.

The customer relationship is also changing. DeBoer described a process of co-imagining, co-designing, co-developing and co-validating. He said this differs sharply from how Micron worked with customers three or four years ago.

Client and data center DRAM​

• LPDDR6: Micron is working with Meta to tune it for data center reliability, serviceability and availability. It targets about 35% lower power than LPDDR5.
• DDR6: Micron plans to develop it with major customers. It targets twice the bandwidth of DDR5.

Neither comes with a date in the reporting. DDR6 is the one that eventually reaches mainstream desktops and servers. Nothing here says when that happens.

NAND: G11 skips a number and doubles density​

Micron's next NAND node is G11 (N170), and there is no G10. StorageReview reports that the density chart in the deck runs G7, G8, G9, G11. DeBoer framed the skipped number as a statement about the size of the step.

Micron's G11 targets:

Tom's Hardware presumes the density doubling would take TLC from 21 to 42 Gb/mm². It also estimates the I/O gain would imply about 5,400 MT/s. Both are the publication's inferences, not Micron figures. StorageReview says the density claim is per unit area. It is therefore as much a wafer-cost statement as a capacity one.

Why wafer-on-wafer bonding matters​

G11 introduces wafer-on-wafer bonding. The memory array is built on one wafer and the peripheral and I/O circuitry on another, then the two are bonded. Tom's Hardware notes that YMTC already uses a similar approach.

DeBoer said Micron held the technique back until it was cost effective. StorageReview says he did not describe the mechanism. Its own reading is that separate wafers decouple array height from what the periphery can tolerate. That is its interpretation, not Micron's statement.

Beyond G11, Micron is investigating high-mobility materials, ultra-dense cell architectures and more efficient data paths. It has given no numbers for those.

AI-oriented NAND and 512 TB SSDs​

Micron described two NAND designs for AI work:

1. High-IOPS AI NAND: SLC-based, with small blocks for vector search, graph analytics and AI context management. The stated range is roughly 25 million to 100 million IOPS depending on configuration. DeBoer called it a major focus for the next couple of years. No test conditions were given.
2. High-Bandwidth AI NAND: TSV-stacked NAND with a logic base die, placed closer to compute. DeBoer said placing it along the GPU shoreline has no merit. He also said these parts cost more and have to be built in partnership with customers.

Micron's roadmap also lists data center SSDs of up to 512 TB. StorageReview stresses that this is a roadmap label, not a product. Micron attached no date, interface or cell type. StorageReview also notes that DapuStor showed a 512 TB QLC drive at FMS in August.

Supply: the part that affects your budget​

StorageReview ties the 2H 2027 ramp to Micron's supply warnings. The roadmap was presented as part of the company's multigenerational plan. On its September 30 earnings call, CEO Sanjay Mehrotra said supply and demand conditions would be much tighter in 2027 and 2028 than in 2026. DeBoer repeated on the webinar that he sees no period when memory is not in short supply over the next two years.

For IT buyers, that means the new nodes are not near-term price relief. G11 and 1δ arrive in the same half-year as a market Micron expects to stay tight. Planning for memory and SSD budgets as if shortages ease soon is a gamble.

What this means for Windows and enterprise readers​

• Servers and AI infrastructure: Custom HBM, vHBM and AI NAND target accelerators. Most Windows Server and Azure customers will meet them as cloud or GPU-server capabilities, not as parts they buy.
• Storage planning: Higher-density G11 drives and 512 TB-class SSDs are future options for dense storage, not near-term purchases.
• Client PCs: DDR6 and LPDDR6 are the relevant long-term items. Micron has given no client timelines.
• Caution: Every performance and power figure here is a target. Production ramps often slip, and yields decide whether density gains become lower prices.

Bottom line​

Micron's message is that memory scaling is shifting from shrinking cells to stacking, bonding and co-designing with customers. Its 4F² decision is a real divergence from three rivals. The only firm production windows are 1δ DRAM and G11 NAND in 2H 2027, and the rest is intent. That is still a useful signal for anyone planning infrastructure, as long as the targets are read as targets.