SiPearl's Rhea1 Samples Land in Bull's BullSequana XH3000 for JUPITER
According to the joint SiPearl–Bull announcement, SiPearl, the fabless designer of European high-performance energy-efficient CPUs built for sovereign supercomputing, AI and data centre, has delivered the first samples of Rhea1 to Bull. Bull has begun integration of Rhea 1 onto its BullSequana XH3000 platform for JUPITER, Europe's first exascale supercomputer. The machine is procured by the EuroHPC Joint Undertaking, the body through which the EU and participating countries fund and coordinate European supercomputers. Forschungszentrum Jülich operates it.
The companies say the shipment will contribute to the development of JUPITER's CPU blade, complementary to the GPU partition, paving the way for the full modular integration of the machine. DigiTimes reported the event separately and described it as moving the processor from bring-up and validation into customer system integration. The Register and Electronics Weekly also covered the delivery, so the event itself is well established.
These are samples, and the timeline makes that clear. SiPearl's corporate boilerplate says Rhea1 will be released at the end of 2026. The supply to JUPITER is also the start of SiPearl's business: the equipment supplied for JUPITER represents SiPearl's first order for Rhea1 and therefore constitutes its first significant revenue. For a company SiPearl says employs about 200 people across France, Spain and Italy, this first deployment is also the first commercial test of whether a European CPU design house can sell a product.
Rhea1 Trades Newer Arm Cores for HBM Memory Bandwidth
On paper, Rhea1 is a memory-bandwidth design. The official description says Rhea1 includes in a single package 80 Arm® Neoverse V1 cores - each with 2 x 256-bit Scalable Vector Extension -, 4 stacks of HBM and 4 DDR5 interfaces. SiPearl's product page adds support for two DIMMs per channel and 104 lanes of PCIe Gen5. SiPearl puts the transistor count at 61 billion and calls Rhea1 the most complex server CPU ever designed in Europe.
The HBM configuration is the detail that matters for workloads. Aroged, relying on SiPearl's technical materials, lists four HBM2e memory stacks (64 GB), and four DDR5 memory channels (2DPC). It also describes the PCIe connectivity as six x16 and two x4 complexes. The Register puts in-package memory bandwidth at 1.8 TB/s. The official material confirms four HBM stacks but does not state that bandwidth figure.
The Register also points out the chip's weakness. Neoverse V1 is an older Arm core design, and the Nvidia Grace CPUs already in JUPITER's Booster use the newer V2 cores. Rhea1's pitch rests on its memory subsystem. SiPearl's product page claims that in-package HBM gives it an "unrivalled byte-per-flop ratio", meaning the chip can move a lot of data for each unit of computation. That is SiPearl's claim, and no published benchmark supports it yet.
The Jülich Supercomputing Centre gives the same reason for using the chip. Director Thomas Lippert said in the announcement that Rhea1's high memory bandwidth "is particularly well suited to applications that benefit from efficient access to large amounts of data." The Register compares it to Fujitsu's A64FX, the HBM-equipped Arm processor behind Japan's Fugaku. It notes that bandwidth-heavy systems like Fugaku have tended to rank higher on the HPCG benchmark than on the more widely cited HPL (LINPACK) test. That comparison describes the design category. It says nothing yet about how Rhea1 performs.
JUPITER's Nvidia GH200 Booster Still Delivers the Exascale Performance
JUPITER's European CPUs arrive after the machine is already running. Jülich says JUPITER became the first European system to officially pass the exascale threshold in November 2025, at 1 exaFLOP/s in 64-bit precision. On the TOP500 list published on 23 June 2026 at ISC in Hamburg, it ranked fifth in the world. Jülich also reported it as the most energy-efficient system in the exascale class.
All of that performance came from American silicon. EuroHPC says JUPITER is built on BullSequana XH3000 and fitted with about 24,000 Nvidia GH200 Grace Hopper Superchips, each pairing a Grace CPU with a Hopper GPU. The TOP500 ranking is based on the LINPACK benchmark, so it measures the GPU Booster's dense floating-point throughput and not the machine's overall balance.
The planned Rhea1 partition is small by comparison. The Register reports that the finished cluster module will have 1,300 nodes with 2,600 processors, delivering an estimated 5 petaFLOPS. That is a fraction of one percent of the Booster's exascale figure. The official announcements do not confirm these node counts or the performance estimate, so treat them as reported plans and not as delivered capacity.
The small size is deliberate. JUPITER is a modular supercomputer: GPU and CPU partitions are built separately so that each job runs on hardware suited to it. Lippert describes Rhea1's role as "complementing the GPU-based Booster with a CPU-based architecture designed for a broad range of complex and data-intensive workloads." Plenty of scientific code has never been ported to GPUs or runs poorly on them. The Rhea1 partition is where that code will run.
"Domestic Silicon" Means European-Designed Rhea1 Chips Built by TSMC
The press release carefully calls Rhea1 the first European-designed CPU deployed in a European-built platform. The key word is "designed". SiPearl's own product page says Rhea1 is manufactured at TSMC. Technetbook reports the chip is built on a TSMC 6 nanometer process. SiPearl's materials opened for this report do not state the process node.
The chip's instruction set and core designs come from Arm, which licenses them. So Rhea1 is European in its SoC design, integration, packaging choices and memory architecture. It is not European in its fabrication or core IP. Bull's platform and EuroHPC's procurement add European system integration and ownership on top. That is a meaningful step up the value chain, but Europe still depends on others for fabs and core designs.
SiPearl makes one sovereignty-related security claim: Rhea1 offers back-door free and kill switch free security. That is the company's own description, and the announcement offers no independent audit or verification method. Organisations weighing sovereign-hardware arguments should read it as a design-control claim from the vendor.
The political framing is openly celebratory. EuroHPC executive director Anders Dam Jensen said "The delivery of the first Rhea1 CPUs marks an important milestone for Europe's supercomputing sovereignty," and credited the European Processor Initiative, the EU-backed consortium where Rhea1 started. Rhea1 was also planned for JUPITER from the beginning, so this delivery closes a gap in a machine that has already been ranked, benchmarked and used by researchers for about a year.
Rhea1 Performance Figures Due This Autumn, General Availability at Year-End
Nobody has published a Rhea1 benchmark. The announcement says that during the ongoing benchmarking phases at SiPearl's laboratories, Rhea1 is delivering very encouraging performance: the early data is strong, and in some cases, performance is exceeding expectations. It also says the performance figures, which are still to be consolidated, will be published this autumn.
That leaves several milestones still to come:
| Milestone | Status |
|---|---|
| First Rhea1 samples delivered to Bull | Done, announced 22 September 2026 |
| Integration into BullSequana XH3000 CPU blades | Started |
| Consolidated Rhea1 performance figures | Promised for autumn 2026 |
| Rhea1 general release | Planned for end of 2026 |
| Full JUPITER cluster module (reported 1,300 nodes, 5 PFLOPS) | Planned; no public completion date |
| Rhea2 in France's Alice Recoque | Announced; not shipped |
Technetbook says successful hardware validation will mark the first major commercial revenue milestone for the startup. Until SiPearl publishes numbers, Rhea1 should be judged by its specifications and not by its speed. On those specifications it is a 2020-era core design with a strong memory subsystem.
SiPearl is also working on its next chip. Its boilerplate says Rhea2 will go into Alice Recoque, France's planned exascale system and the second European exascale machine EuroHPC has procured. The Register reports that Alice Recoque will pair Rhea2 in its CPU partition with AMD MI430X accelerators in its GPU partition. That repeats JUPITER's approach: a European CPU partition next to a US accelerator partition.
What This Means for HPC Users, Arm Developers and IT Buyers
Most Windows desktop and enterprise readers don't need to do anything now. This matters for three groups: researchers and developers who will run code on JUPITER's CPU partition, software teams building Arm server builds, and public-sector IT buyers tracking European sovereign-hardware procurement.
For developers, Rhea1 is another sign that serious HPC and data-centre compute runs on Arm. SiPearl pitches it on the "Arm mature software ecosystem" and says it is supported by a range of compilers, libraries and tools. Code that already builds for Arm Neoverse targets, including Nvidia Grace, is closer to running on Rhea1 than x86-only code. Using the chip's two 256-bit SVE (Scalable Vector Extension) units per core will take vector-aware compilation. That last point is general Arm practice, not a Rhea1-specific procedure SiPearl has documented.
The Seine Reference Server, which SiPearl says comes in single-socket-plus-two-GPU and dual-socket Rhea1 configurations, is intended for validation, software porting and customer testing. Teams wanting early access to the chip should go through that platform rather than JUPITER itself, which will be available only through EuroHPC and Jülich allocation processes once the partition is in service.
- SiPearl delivered Rhea1 samples to Bull on 22 September 2026, and integration into JUPITER's BullSequana XH3000 CPU blades has started, but the CPU partition is not yet in service.
- Rhea1 pairs 80 Arm Neoverse V1 cores with four HBM stacks and four DDR5 channels, so its case depends on memory bandwidth and not on having the newest core design.
- No independent Rhea1 benchmarks exist yet, and SiPearl has promised consolidated performance figures this autumn and general release at the end of 2026.
- JUPITER's fifth-place TOP500 ranking and exascale performance come from roughly 24,000 Nvidia GH200 superchips, and the reported 5-petaFLOPS Rhea1 partition will not change that ranking in any meaningful way.
- Rhea1 is European-designed but manufactured at TSMC on Arm-licensed cores, so sovereignty claims about it cover design and integration, not fabrication.
- Researchers with CPU-bound, bandwidth-sensitive codes that don't suit GPUs are the users most likely to benefit once the cluster module goes live.
JUPITER will soon run Europe's first home-designed server CPU inside a European-built system, but it remains an Nvidia machine where performance rankings are concerned. The Rhea1 partition reported by The Register is small and will run CPU-bound work, and its value is still unproven until SiPearl publishes the benchmarks it has promised for this autumn. Those figures, followed by Rhea1's planned general release at the end of the year, will show whether this delivery produces a useful HPC processor or mainly a sovereignty milestone ahead of Rhea2's debut in Alice Recoque.