Tom’s Hardware, HotHardware and VideoCardz each reported the 256-core configuration after Intel’s August 24 Hot Chips session. Intel’s own presentation framing is broader: Diamond Rapids is its next Xeon platform for enterprise-scale AI and conventional server workloads, built with Intel 18A-P manufacturing, Foveros Direct 3D stacking and UCIe-S die-to-die links. The critical update is the architecture beneath that marketing: Intel is changing how a high-end Xeon is assembled and how its cores reach shared cache, memory and I/O.
For Windows Server administrators, virtual infrastructure teams and buyers planning 2027 refresh cycles, Diamond Rapids now looks less like a straightforward core-count bump over Granite Rapids and more like Intel’s attempt to remove memory bandwidth, cache capacity and package-scale communication as bottlenecks in dense P-core servers. It has reached numerical parity with AMD’s announced top-end 256-core EPYC Venice configuration on core count and memory-bandwidth headline, but Intel has offered no application performance comparisons between the platforms.
Sixteen CPU Tiles Feed Four 320 MB Cache Bases
The flagship Diamond Rapids package is arranged as four Compute Building Blocks. Each block combines four 16-core CPU chiplets on a base tile, yielding 64 P-cores per block and 256 across the full processor. The CPU chiplets use Intel 18A-P, while ComputerBase reports the four base tiles are made on Intel 3-T, a process variant optimized for through-silicon vias used in 3D stacking.
Each base tile carries 320 MB of shared L3 cache. Across the four blocks, that supplies 1.28 GB of last-level cache, or an arithmetic average of 5 MB per core. That does not mean every core has a private 5 MB allocation: the cache is organized in four physical regions paired with groups of 64 cores. The effective behavior for applications will depend on cache-access latency, coherence traffic and workload placement—details Intel did not publish at Hot Chips.
That distinction is more than packaging trivia. Database engines, in-memory analytics, virtualization hosts and CPU-side AI inference can all gain from a much larger shared cache if the working set stays local enough to benefit. But a cache total alone cannot establish a performance gain. Intel did not disclose L2-cache sizes, cache latency, cache bandwidth, clock rates, or any benchmark results for Diamond Rapids’ new P-cores.
Intel’s decision to use 16 smaller compute dies also makes manufacturing sense for a 256-core flagship. Smaller chiplets can reduce the yield risk associated with building one enormous leading-edge compute die, while Foveros Direct 3D allows Intel to stack them tightly over the cache-bearing base tiles. The tradeoff is that Intel must make communication among all of those blocks predictable enough that the modular design does not create uneven behavior for software that spans the socket.
UCIe-S Replaces EMIB for the Long Links
Intel is retaining Foveros Direct 3D for the vertical connection between a CPU chiplet and its base tile. The company is using UCIe-S rather than EMIB for the horizontal links between the four Compute Building Blocks and the two Fabric Hub tiles in the center of the package.
That is a meaningful architectural choice. EMIB, Intel’s embedded bridge technology, has been a prominent part of past multi-tile Xeons, including Sapphire Rapids and Granite Rapids. In Diamond Rapids, the central fabric hubs connect to every compute block over UCIe-S links routed through the package substrate. Intel told Hot Chips attendees that this gave it low-latency, uniform connections to all memory hubs over the required distance.
The key word is uniform. A 256-core package does not simply need a fast connection between neighboring chiplets; it needs an orderly way for any compute block to reach memory, I/O and other cache domains without widely different path lengths. Tom’s Hardware reported that each Compute Building Block connects to both Fabric Hub tiles, creating redundant paths to the centralized fabric rather than assigning each core region to one isolated I/O side.
This is also Intel’s most concrete public use yet of UCIe-S in a high-end server CPU. UCIe, or Universal Chiplet Interconnect Express, is an industry interconnect specification intended to make die-to-die links more standardized. Diamond Rapids does not establish that buyers will be able to mix third-party chiplets into a Xeon package; Intel has described the processor as built exclusively on its own technology. Here, UCIe-S is an internal package-level transport choice, not an announced plug-and-play chiplet program.
The Fabric Hub tiles consolidate the memory and I/O functions that Intel has moved away from the edges of the package. They also contain an on-die snoop filter, according to ServeTheHome’s account of the session. A snoop filter tracks cache-coherence state; moving that directory work onto the processor can reduce coherence traffic and avoid using DRAM capacity for directory storage. This is a particularly relevant change for multi-socket systems and large virtualized fleets, where cores frequently share memory and must maintain a consistent view of it.
Sixteen Memory Channels Raise the Platform Ceiling
Diamond Rapids will support 16 memory channels per socket, with DDR5 speeds up to 8,000 MT/s and MRDIMM speeds up to 12,800 MT/s. Intel quotes up to 1.6 TB/s of memory bandwidth, and it is exposing 128 lanes configurable across PCIe 6.0, CXL 3.0 and UPI 3, plus eight PCIe 4.0 lanes for platform use.
Those numbers place the platform emphasis squarely on feeding more cores. Intel’s top Granite Rapids-AP Xeons provide up to 12 DDR5 channels and 128 P-cores. Doubling the core count without substantially more memory bandwidth would leave many throughput workloads constrained by memory access; Diamond Rapids answers that with 16 channels and faster MRDIMM support.
The caveat is that the 1.6 TB/s figure represents a platform maximum, not an automatic outcome of installing ordinary DIMMs. Organizations that want the top bandwidth will need qualified MRDIMMs, motherboard support and memory configurations that match Intel’s validated speeds. Those modules can change server acquisition costs, availability planning and operational tuning. Intel has not released a server-platform bill of materials, motherboard list or pricing.
The I/O allocation also has practical implications for storage-heavy and accelerator-heavy servers. PCIe 6.0 and CXL 3.0 give system vendors a route to faster NVMe, network, FPGA, GPU and memory-expansion designs without requiring every workload to fit into local DDR5. Yet Intel has not identified the first OEM systems, CXL memory configurations or PCIe lane splits. Those omissions matter more than the raw lane count for administrators deciding whether a future system can consolidate existing NIC, storage and accelerator cards.
AVX 10.2 and APX Put Software Back on the Critical Path
Diamond Rapids adds AVX 10.2, Advanced Matrix Extensions updates and Advanced Performance Extensions, or APX. The instruction-set changes are a longer-term software story than a day-one infrastructure feature.
According to Intel’s Hot Chips disclosures, AVX 10.2 provides a converged 256-bit vector model intended to operate across both P-core and E-core designs, while Diamond Rapids itself is a P-core Xeon. APX expands the general-purpose x86 register file from 16 to 32 registers and introduces additional instruction encodings. Intel says recompiling software for APX can reduce loads and stores without source-code changes.
That last claim needs careful reading in enterprise environments. Recompiling without source changes still requires a toolchain that targets APX, software vendors willing to ship optimized builds, testing, and deployment in production environments. Existing Windows Server applications will remain compatible with x86, but compatibility is not the same as receiving an APX benefit. Administrators should expect the first performance gains to arrive unevenly through updated compilers, database engines, analytics libraries and hypervisor-adjacent tooling.
Intel is also retaining its hardware accelerator approach through QuickAssist Technology, Data Streaming Accelerator and In-Memory Analytics Accelerator complexes, alongside AMX. Those blocks could help compression, encryption, data movement and analytics workloads, but Intel did not supply Diamond Rapids throughput figures or explain which accelerators appear in every SKU. Buyers should not treat the accelerator list as a guarantee that a lower-cost Xeon 7 model will mirror the flagship’s capabilities.
18A-P Is the Manufacturing Bet, Not a Product Benchmark
Intel’s decision to place the CPU chiplets on 18A-P gives Diamond Rapids an additional strategic role: it will be a major server validation of Intel’s performance-enhanced 18A process family. Intel announced in June that 18A-P had entered risk production and claimed up to 9% higher performance at equal power or 18% lower power at equal performance versus baseline 18A.
Those are process-level claims, not promised Xeon 7 gains over Granite Rapids or AMD EPYC. They cannot be translated into a server-performance forecast without knowing the Diamond Rapids core design, frequency targets, voltage behavior, memory subsystem efficiency, cache latency and thermal envelope. Intel also has not published the P-core microarchitecture details that would let customers assess single-thread performance, branch behavior or vector execution.
The timing is clearer than the performance picture. Intel has confirmed Diamond Rapids for 2027, while AMD has already publicized a 256-core EPYC Venice design with 1.6 TB/s of memory bandwidth. Intel has matched those two top-line specifications on paper, but its product will arrive on a different schedule and neither vendor’s headline figures substitute for independent workload testing.
Intel’s Hot Chips disclosure establishes the technical direction: a 256-core Xeon built from 16 18A-P compute dies, backed by 1.28 GB of shared cache and a centralized UCIe-S fabric. The remaining milestones are the ones procurement teams need before treating it as a refresh target—actual SKU tables, socket and platform requirements, DDR5 and MRDIMM validation, power limits, OEM availability, and benchmarks that show whether this highly modular package performs consistently under real Windows Server, Linux, database and virtualization loads.
