TSMC’s advanced packaging capacity remains under pressure from AI and high-performance computing demand, with orders reportedly spilling over to Intel and Taiwanese outsourced semiconductor assembly and test firms. Wccftech, citing Commercial Times, says customers unable to secure enough CoWoS capacity are increasingly evaluating Intel’s EMIB technology and services from ASE, SPIL, Powertech and KYEC.
CoWoS—short for Chip-on-Wafer-on-Substrate—is a key production step for modern AI accelerators. It enables large logic dies and stacks of high-bandwidth memory to be combined in a single package, making it a limiting factor for products such as data-center GPUs and custom AI chips even when leading-edge silicon wafers are available.
The report is credible in broad terms: TSMC’s annual reporting has described strong growth in CoWoS demand driven by AI chips, while CEO C.C. Wei said at the company’s June 2026 shareholders meeting that demand would take time to satisfy. TrendForce separately reported in June that the CoWoS supply-demand gap could narrow from roughly 20% to 10% by the end of 2026 as new capacity comes online.
That does not mean every displaced CoWoS order can simply move to another supplier. CoWoS, Intel’s EMIB, and the various offerings from Taiwanese packaging houses use different interconnect, substrate and assembly approaches. Moving a design can require engineering work, qualification and a reliable supply of HBM memory and substrates. Capacity availability alone is not enough.
Wccftech’s report repeats earlier claims that Nvidia could send advanced-packaging work for its future Feynman-generation GPUs to Intel. That remains unconfirmed by Nvidia, Intel and TSMC. The more immediate opportunity appears to be custom accelerators and cloud-provider ASICs, where packaging choices can be designed around available manufacturing capacity earlier in the development cycle.
Taiwan’s OSAT suppliers are also positioned to gain from overflow demand, although they are not wholesale replacements for TSMC’s integrated fabrication-and-packaging model. Their role could include package assembly, testing and alternative 2.5D integration flows for customers willing to qualify them.
For IT buyers, the practical result is that availability of AI servers may increasingly depend on packaging allocations and vendor qualification, not just GPU model announcements.
Google has reportedly used TSMC CoWoS packaging across TPU generations three through eight. A move to EMIB-T would therefore require substantial re-engineering and qualification, reinforcing that the reported decision is likely driven by more than short-term capacity pressure. Potential factors include supply-chain diversification, cost, package-scale requirements and EMIB-T’s vertical power-delivery features.
The report does not establish that EMIB-T is universally superior to TSMC’s CoWoS-L. CoWoS-L retains an advantage in dense, package-wide routing, while Intel’s bridge-based approach may offer different power-integrity and mechanical trade-offs. Google, Intel and TSMC have not publicly confirmed the Humufish packaging arrangement.
For enterprise AI buyers, a hyperscaler adopting an Intel packaging flow would be an early signal that alternative advanced-packaging ecosystems are becoming viable for major accelerator programs. That could eventually reduce dependence on a single CoWoS supply pipeline, though it will not produce an immediate increase in available AI servers.
CoWoS—short for Chip-on-Wafer-on-Substrate—is a key production step for modern AI accelerators. It enables large logic dies and stacks of high-bandwidth memory to be combined in a single package, making it a limiting factor for products such as data-center GPUs and custom AI chips even when leading-edge silicon wafers are available.
A packaging bottleneck, not a conventional chip shortage
The report is credible in broad terms: TSMC’s annual reporting has described strong growth in CoWoS demand driven by AI chips, while CEO C.C. Wei said at the company’s June 2026 shareholders meeting that demand would take time to satisfy. TrendForce separately reported in June that the CoWoS supply-demand gap could narrow from roughly 20% to 10% by the end of 2026 as new capacity comes online.That does not mean every displaced CoWoS order can simply move to another supplier. CoWoS, Intel’s EMIB, and the various offerings from Taiwanese packaging houses use different interconnect, substrate and assembly approaches. Moving a design can require engineering work, qualification and a reliable supply of HBM memory and substrates. Capacity availability alone is not enough.
Intel has an opening—but no confirmed Nvidia win
Intel Foundry has been pitching EMIB and Foveros packaging as alternatives for large multi-die designs. EMIB uses embedded silicon bridges rather than a full silicon interposer, and Intel says its advanced packaging roadmap supports increasingly large AI and HPC packages.Wccftech’s report repeats earlier claims that Nvidia could send advanced-packaging work for its future Feynman-generation GPUs to Intel. That remains unconfirmed by Nvidia, Intel and TSMC. The more immediate opportunity appears to be custom accelerators and cloud-provider ASICs, where packaging choices can be designed around available manufacturing capacity earlier in the development cycle.
Taiwan’s OSAT suppliers are also positioned to gain from overflow demand, although they are not wholesale replacements for TSMC’s integrated fabrication-and-packaging model. Their role could include package assembly, testing and alternative 2.5D integration flows for customers willing to qualify them.
Why Windows and enterprise buyers should care
This is principally a data-center supply-chain issue, not a near-term change for Windows PCs. But advanced packaging capacity affects when AI accelerators reach server vendors, cloud providers and enterprise infrastructure projects. A constrained CoWoS pipeline can delay deployments or keep accelerator pricing elevated; more qualified packaging suppliers should eventually improve supply resilience.For IT buyers, the practical result is that availability of AI servers may increasingly depend on packaging allocations and vendor qualification, not just GPU model announcements.
Update: Google reportedly selects Intel EMIB-T for next-generation TPU (July 16, 2026)
Tom’s Hardware reports that Google plans to use Intel’s EMIB-T advanced packaging for its ninth-generation TPU, codenamed Humufish, citing SemiAnalysis. If confirmed, it would be a notable concrete design win for Intel Foundry’s packaging business—not merely evidence that customers are evaluating alternatives to constrained CoWoS capacity.Google has reportedly used TSMC CoWoS packaging across TPU generations three through eight. A move to EMIB-T would therefore require substantial re-engineering and qualification, reinforcing that the reported decision is likely driven by more than short-term capacity pressure. Potential factors include supply-chain diversification, cost, package-scale requirements and EMIB-T’s vertical power-delivery features.
The report does not establish that EMIB-T is universally superior to TSMC’s CoWoS-L. CoWoS-L retains an advantage in dense, package-wide routing, while Intel’s bridge-based approach may offer different power-integrity and mechanical trade-offs. Google, Intel and TSMC have not publicly confirmed the Humufish packaging arrangement.
For enterprise AI buyers, a hyperscaler adopting an Intel packaging flow would be an early signal that alternative advanced-packaging ecosystems are becoming viable for major accelerator programs. That could eventually reduce dependence on a single CoWoS supply pipeline, though it will not produce an immediate increase in available AI servers.
References
- Primary source: Wccftech
Published: 2026-07-12T11:40:12+00:00
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